Patents by Inventor Ragu Sridhar

Ragu Sridhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8456204
    Abstract: Methods and systems directed toward a PLL circuit including a local lock detector receiving an error signal and providing a lock signal, and a charge pump for receiving the error signal and providing a charge signal. A loop filter provides a first loop filter bandwidth and a second loop filter bandwidth. The loop filter includes a first low-pass filter configured to receive the charge and lock signals, alter a filter characteristic in response to the lock signal, and provide a first filter signal. The loop filter includes a second low-pass filter configured to receive the first filter and lock signals, alter a filter characteristic in response to the lock signal, and provide a loop filter signal. The PLL circuit includes a VCO for receiving the loop filter signal and providing an output signal, and a divider for receiving the output signal and dividing it to provide the reference signal.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: June 4, 2013
    Assignee: NXP B.V.
    Inventors: Benedykt Mika, Ragu Sridhar, Ron Osgood, Rohini Abhyankar, Amrita Deshpande
  • Publication number: 20110187425
    Abstract: Methods and systems directed toward a PLL circuit (100) including a local lock detector (180) receiving an error signal and providing a lock signal, and a charge pump (120) for receiving the error signal and providing a charge signal. A loop filter provides a first loop filter bandwidth and a second loop filter bandwidth. The loop filter includes a first low-pass filter (130) configured to receive the charge and lock signals, alter a filter characteristic in response to the lock signal, and provide a first filter signal. The loop filter includes a second low-pass filter (150) configured to receive the first filter and lock signals, alter a filter characteristic in response to the lock signal, and provide a loop filter signal. The PLL circuit includes a VCO (160) for receiving the loop filter signal and providing an output signal, and a divider (170) for receiving the output signal and dividing it to provide the reference signal.
    Type: Application
    Filed: June 21, 2006
    Publication date: August 4, 2011
    Applicant: NXP B.V.
    Inventors: Benedykt Mika, Ragu Sridhar, Ron Osgood, Rohini Abhyankar, Amrita Deshpande