Abstract: An apparatus is described. The apparatus includes a liquid cooling system having multiple heat-exchangers and multiple valves. The multiple valves are to enable/disable participation of individual ones of the heat-exchangers within the liquid cooling system. The apparatus includes an information keeping device to store information that correlates a number of the multiple heat exchangers to be enabled to realize one or more semiconductor chips' target temperature for a power consumption of the one or more semiconductor chips for a plurality of combinations of target temperature and power consumption.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: The present description relates to the field of microelectronic device retention mechanisms and, more particularly, to a quick release retention mechanism including a base plate, a load plate and a biasing mechanism adapted to apply a desired load and to allow rapid insertion and extraction of microelectronic devices from sockets.

Abstract: The present description relates to the field of microelectronic device retention mechanisms and, more particularly, to a quick release retention mechanism including a base plate, a load plate and a biasing mechanism adapted to apply a desired load and to allow rapid insertion and extraction of microelectronic devices from sockets.