Patents by Inventor Rahoul Varma

Rahoul Varma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060288170
    Abstract: A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 21, 2006
    Applicant: ARM Limited
    Inventors: Rahoul Varma, David McHale, Philippe Raphalen, Christophe Evrard, Cedric Airaud
  • Publication number: 20060184804
    Abstract: A data processing apparatus operable to access data values, each data value being associated with a respective address value is disclosed.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 17, 2006
    Applicant: ARM Limited
    Inventors: Rahoul Varma, Marc Wicks, Gareth Duncan, David McHale, Mike Livesley
  • Publication number: 20060112310
    Abstract: The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 25, 2006
    Applicant: ARM LIMITED
    Inventors: David McHale, Rahoul Varma, Marc Wicks, Mike Livesley, Gareth Duncan