Patents by Inventor Rahul G. Patel

Rahul G. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7599889
    Abstract: An “ownership tag” in a special area of memory of a computer system identifies an owner of the computer system by displaying the ownership tag during initialization of the computer system. The ownership tag may be presented during the installation and execution of the Basic Input Output System. (BIOS) preferably during Power on Self Test (POST) process. An administrator may access the ownership tag by interrupting the process by pressing the an appropriate key, which transitions the computer to an administrator set up mode. An administrator able to enter the administrator password may then alter the contents of the protected memory, changing the ownership tag. The ownership tag is preferably stored in a region of memory not accessible to a typical user, but accessible to an administrator aware of the administrator password. The ownership tag is stored in a flash memory, which is very difficult to remove from the system board, or to modify without administrator-level security access.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: October 6, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul J. Broyles, III, Rahul G. Patel, Mark A. Piwonka
  • Publication number: 20090198832
    Abstract: In one embodiment, a network device (e.g., a master controller) may detect an event on a current path in a computer network from a local network domain to a destination address prefix of a remote domain. In response, the device may dynamically (e.g., intelligently) determine a trace target destination address within the destination address prefix, and may perform (or request performance of) a Traceroute of the current path and a selection of alternate paths in the network from the local network domain to the trace target, where the Traceroute is adapted to obtain per-hop measurements along the respective traced path. The measurements may then be stored, for example, to be used for optimal path selection, fault identification reporting, etc.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventors: Pritam Shah, Dana Blair, Rahul G. Patel
  • Patent number: 7257560
    Abstract: A technique for efficiently and accurately minimizing costs associated with services provided by a plurality of service providers (SPs) that bill for their services based on a tiered cost structure. Target tiers are generated based on the utilization of the SPs' services and the SPs' cost structures. Utilization of the SPs' services is monitored. A momentary target utilization rate (MTUR) is generated for each SP based on the cumulated utilization of the SP's service and the SP's target tier. Utilization of the SPs' services is distributed based on the generated MTURs in a manner that minimizes cost. If the utilization of the SPs' services indicates the MTURs have been exceeded, new target tiers and MTURs are generated and utilization of the SPs' services is redistributed among the SPs in a manner that minimizes cost.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 14, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Philip C. Jacobs, Rahul G. Patel
  • Patent number: 6873333
    Abstract: A computer system has a selectable set-up feature to adjust the display screen image presented during power on self test, or POST. The computer memory contains two sets of information that can be presented on the video display screen. An application of power to the computer system, a first form of information from a first video memory area is normally presented to the computer output device. This information is simpler in format, requiring less memory. Also, upon the application of power to the computer system, flags or semaphores direct substantially all of a detailed or verbose screen information from initialization, configuration, or other boot-time routines to a second video memory area while information in the first video memory area is presented on the display. Upon receiving one of a predetermined set of commands, the computer system switches from the first display to the second display, presenting the second verbose screen information on the video screen.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rahul G. Patel, Paul J. Broyles
  • Patent number: 6832320
    Abstract: An “ownership tag” in a special area of memory of a computer system identifies an owner of the computer system by displaying the ownership tag during initialization of the computer system. The ownership tag may be presented during the installation and execution of the Basic Input Output System (BIOS) preferably during Power on Self Test (POST) process. An administrator may access the ownership tag by interrupting the process by pressing the an appropriate key, which transitions the computer to an administrator set up mode. An administrator able to enter the administrator password may then alter the contents of the protected memory, changing the ownership tag. The ownership tag is preferably stored in a region of memory not accessible to a typical user, but accessible to an administrator aware of the administrator password. The ownership tag is stored in a flash memory, which is very difficult to remove from the system board, or to modify without administrator-level security access.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: December 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul J. Broyles, III, Rahul G. Patel, Mark A. Piwonka
  • Patent number: 6363473
    Abstract: A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use the simulated stack to store a data value for subsequent retrieval and use. The non-general purpose register set may include memory type range registers (MTRRs). One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions provide for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of simulated stack.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: March 26, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Robert J. Volentine, Rahul G. Patel