Patents by Inventor Rahul K. Nadkarni
Rahul K. Nadkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9557378Abstract: Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device.Type: GrantFiled: July 20, 2012Date of Patent: January 31, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jeanne P. Bickford, Vikram Iyengar, Rahul K. Nadkarni, Pascal A. Nsame
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Patent number: 8873269Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.Type: GrantFiled: March 18, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Rahul K. Nadkarni, Daniel R. Baratta, Konark Patel, Hoan H. Nguyen
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Publication number: 20140268985Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Rahul K. Nadkarni, Daniel R. Baratta, Konark Patel, Hoan H. Nguyen
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Publication number: 20140024145Abstract: Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: International Business Machines CorporationInventors: JEANNE P. BICKFORD, Vikram Iyengar, Rahul K. Nadkarni, Pascal A. Nsame
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Patent number: 8233302Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.Type: GrantFiled: January 4, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
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Publication number: 20110096582Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
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Patent number: 7924588Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.Type: GrantFiled: December 3, 2007Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
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Patent number: 7619923Abstract: A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.Type: GrantFiled: December 5, 2007Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Rahul K. Nadkarni
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Publication number: 20090147590Abstract: A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.Type: ApplicationFiled: December 5, 2007Publication date: June 11, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Correale, JR., Rahul K. Nadkarni
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Publication number: 20090141528Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.Type: ApplicationFiled: December 3, 2007Publication date: June 4, 2009Inventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
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Publication number: 20090141530Abstract: A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.Type: ApplicationFiled: April 28, 2008Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wisort
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Patent number: 7515449Abstract: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.Type: GrantFiled: September 15, 2006Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Igor Arsovski, Rahul K. Nadkarni, Reid A. Wistort
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Publication number: 20080080223Abstract: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs.Type: ApplicationFiled: September 15, 2006Publication date: April 3, 2008Inventors: Igor Arsovski, Rahul K. Nadkarni, Reid A. Wistort
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Patent number: 6920525Abstract: A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.Type: GrantFiled: July 19, 2002Date of Patent: July 19, 2005Assignee: International Business Machines CorporationInventors: Thomas B. Chadwick, Tarl S. Gordon, Rahul K. Nadkarni, Michael R. Ouellette, Jeremy Rowland
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Publication number: 20040015651Abstract: A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.Type: ApplicationFiled: July 19, 2002Publication date: January 22, 2004Applicant: International Business Machines CorporationInventors: Thomas B. Chadwick, Tarl S. Gordon, Rahul K. Nadkarni, Michael R. Ouellette, Jeremy Rowland
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Patent number: 6597596Abstract: A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.Type: GrantFiled: November 1, 2002Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Tarl S. Gordon, Rahul K. Nadkarni
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Publication number: 20030065880Abstract: A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.Type: ApplicationFiled: November 1, 2002Publication date: April 3, 2003Inventors: Tarl S. Gordon, Rahul K. Nadkarni
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Patent number: 6512684Abstract: A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.Type: GrantFiled: June 11, 2001Date of Patent: January 28, 2003Assignee: International Business Machines CorporationInventors: Tarl S. Gordon, Rahul K. Nadkarni
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Publication number: 20020196648Abstract: A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.Type: ApplicationFiled: June 11, 2001Publication date: December 26, 2002Applicant: International Business Machines CorporationInventors: Tarl S. Gordon, Rahul K. Nadkarni
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Patent number: 6430072Abstract: A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.Type: GrantFiled: October 1, 2001Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Thomas B. Chadwick, Rahul K. Nadkarni, Michael R. Ouellette, Jeremy P. Rowland