Abstract: Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

Abstract: Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

Abstract: Systems and methods for pulse generation in a dual voltage domain include a first and a second voltage aware branch sensitive to a low voltage domain. The first voltage aware branch includes an inverter in the low voltage domain for delaying a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain. The second voltage aware branch includes a delay element in the low voltage domain for extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.

Abstract: Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.