Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.

Abstract: A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.

Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.

Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Abstract: A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A computer implemented method for correcting early mode slack fails in an electronic circuit can include generating a logical description of an electronic circuit having a path from first circuit to a second circuit. The method then include compiling the logical description into a technology specific representation of the circuit. The method may further include determining that the path has an early mode slack fail. The method may be continued by identifying, in response to determining that a second path has a first early mode slack fail, a complex logic gate located in the second path and having an output coupled to the input of the second circuit that can be decomposed into two or more logic gates. The method may then conclude by decomposing, by processor, the complex logic gate into a two or more logic gates to address the early mode slack fail.

Abstract: A computer implemented method for correcting early mode slack fails in an electronic circuit can include generating a logical description of an electronic circuit having a path from first circuit to a second circuit. The method then include compiling the logical description into a technology specific representation of the circuit. The method may further include determining that the path has an early mode slack fail. The method may be continued by identifying, in response to determining that a second path has a first early mode slack fail, a complex logic gate located in the second path and having an output coupled to the input of the second circuit that can be decomposed into two or more logic gates. The method may then conclude by decomposing, by processor, the complex logic gate into a two or more logic gates to address the early mode slack fail.

Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Abstract: Circuitry including a logic circuitry portion and a delay circuitry portion, with the circuitry having the following features: (i) the logic circuitry is designed to receive a set of input signals including a first input signal and a second input signal; and (ii) the delay circuitry portion includes a transistor connected so that the first input signal gates the second input signal. In some embodiments, the first and second input signals are chosen because it is expected that the second input signal will arrive at the circuitry before the first input signal so that the gating of the second signal by the first signal will cause the logic circuitry portion to receive the first and second signals at substantially the same time. Also, circuitry where a first output signal from a logic circuitry portion is gated by a second output signal.

Abstract: Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

Abstract: Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

Abstract: A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.