Abstract: A software defined transmit architecture includes a plurality of individually selectable components that can be selectively enabled to transmit a data signal that complies with any of a plurality of transmission standards. The software defined transmit architecture comprises components that can be enabled by associated logic to transmit, for example, communications signals that comply with the global system for mobile communications (GSM), enhanced data rates for GSM evolution (EDGE), which employs TDMA, and wide band code division multiple access (WCDMA) transmission standards. A single transmit architecture supports multiple transmission standards, thus minimizing the number of components in a multi-band, multi-mode portable transceiver, while reducing the number of active components.

Abstract: A mixing system divides a local oscillator (“LO”) signal into two signals having a predetermined phase difference, mixes each of the two signal with an input signal to produce a mixed signal, and then combines the mixed signals to produce an output signal having substantially no third-order mixing products.

Abstract: An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.

Abstract: A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated information signal. The method includes the steps of delaying the local oscillator signal in a plurality of incremental odd and even delay steps to form respective sets of odd and even modulator signals, said odd set of modulator signals together forming the first modulation signal and said even set forming the second modulation signal for quadrature subharmonic modulation of the quadrature amplitude modulated information signal and controlling a magnitude of the incremental delays based upon a predetermined phase offset between the local oscillator signal and a last delay step of the incremental delay steps.

Abstract: A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated information signal. The method includes the steps of delaying the local oscillator signal in a plurality of incremental odd and even delay steps to form respective sets of odd and even modulator signals, said odd set of modulator signals together forming the first modulation signal and said even set forming the second modulation signal for quadrature subharmonic modulation of the quadrature amplitude modulated information signal and controlling a magnitude of the incremental delays based upon a predetermined phase offset between the local oscillator signal and a last delay step of the incremental delay steps.

Abstract: Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator.

Abstract: Systems for reducing the parasitic effects of a transistor-based switch are provided. In one such system provides a transistor circuit for implementing a switch having reduced parasitic effects. In general, the transistor circuit comprises a first switch node, a second switch node, a third switch node, a transistor device, and a circuit configured to reduce the parasitic characteristics of the transistor device. The first switch node is for connecting to one node of an external circuit. The second switch node is for connecting to a second node of an external circuit. The transistor device is a three-terminal device. The first terminal is connected to the first switch node. The second terminal is connected to the second switch node. The third terminal is for receiving a control signal that operates the transistor circuit as a switch by controlling the electrical connectivity between the first terminal and the second terminal. The third switch node is for receiving the control signal.

Abstract: A subharmonic mixer and a method of downconverting a received radio frequency signal is described. The subharmonic mixer of the present invention uses two stacks of switching cores with high order symmetry to reduce unwanted harmonic generation and uses transistors to improve headroom.

Abstract: A programmable frequency divider capable of a 50% duty cycle at odd and even integer division ratios. In one embodiment, the frequency divider is configured to produce an output signal having a period equal to a division ratio N times a period of a clock signal, and the division number N is a programmable variable which bears the following relationship to the number F of required storage elements: F = N + P 2 , where P is 1 if the division ratio is odd, and 0 if the division ratio is even.

Abstract: A translation loop signal upconverter is disclosed. Embodiments of the invention minimize nth order harmonics and spurious tones in the radio frequency output spectrum of a portable transceiver. In one embodiment, the invention is a signal upconverter, comprising a modulator configured to develop a modulated intermediate frequency (IF) signal at a fundamental frequency, the modulated IF signal also including a plurality of nth order components, a synchronous oscillator configured to receive the modulated IF signal, the synchronous oscillator also configured to operate at the fundamental frequency of the modulated IF signal, thereby providing an IF signal substantially free of the nth order components, and a translation loop having a phase locked loop, the translation loop configured to receive the IF signal output of the synchronous oscillator, and supply a radio frequency (RF) output signal to a power amplifier.

Abstract: A system is disclosed for transmitting and receiving signals. The system includes the use of a frequency plan table a system for creating the frequency plan table. The frequency plan table relates carrier frequency channels to the operation of a synthesizer and a plurality of programmable frequency dividers in a locked loop. In a transmitter, a first programmable frequency divider accepts a reference signal and produces a comparison signal. A mixer accepts the reference signal and a transmission signal and produces a loop signal. A second programmable frequency divider accepts the loop signal and produces a loop signal having a divided intermediate frequency signal. A phase detector compares the comparison signal and the loop signal having a divided intermediate frequency and produces an output that controls a variable controlled oscillator. The variable controlled oscillator produces a modulated transmission signal.

Abstract: An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.

Abstract: A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated information signal. The method includes the steps of delaying the local oscillator signal in a plurality of incremental odd and even delay steps to form respective sets of odd and even modulator signals, said odd set of modulator signals together forming the first modulation signal and said even set forming the second modulation signal for quadrature subharmonic modulation of the quadrature amplitude modulated information signal and controlling a magnitude of the incremental delays based upon a predetermined phase offset between the local oscillator signal and a last delay step of the incremental delay steps.

Abstract: A direct conversion receiver for receiving a first input signal and directly downconverting it to baseband frequencies. The receiver includes a frequency translator which is responsive to a phase-split input signal having 2n components, wherein n is an integer greater than 1. The phase-split signal has a period T which is about n times the period of the first input. The frequency translator alternates, at a rate of about 2n/T, between switching the first input signal to a first output, and switching the first signal to a second output. A preprocessor is available to improve the switching characteristics of the phase-split input signal.

Abstract: A transmitter for a wireless handset having a modified translation loop architecture. The transmitter includes a VCO that generates a modulated transmit signal having a frequency fTx, and a modulated signal source that generates a modulated LO signal with a frequency fLO. A mixer mixes the transmit signal with the LO signal to produce an IF signal having a frequency fIF. A first divider divides the LO signal frequency fLO by an integer M to generate a first comparison signal having a frequency fCF. A second divider divides the IF signal frequency fIF, after it is multiplied by an integer K, by an integer N to generate a second comparison signal having a frequency fCF. The transmit and LO signal frequencies have the relationship 1 f Tx = f LO ⁢ KM ± N M .

Abstract: A direct conversion receiver for receiving a first input signal and directly downconverting it to baseband frequencies. The receiver includes a frequency translator which is responsive to a phase-split input signal having 2n components, wherein n is an integer greater than 1. The phase-split signal has a period T which is about n times the period of the first input. The frequency translator alternates, at a rate of about 2n/T, between switching the first input signal to a first output, and switching the first signal to a second output. A preprocessor is available to improve the switching characteristics of the phase-split input signal.

Abstract: The DC offset compensator compensates DC offsets resulting from interferor self mixing and interferor interaction with even-order nonlinearities. In one embodiment, the DC offset compensator resides in a mobile communication device. A radio frequency (RF) communication signal is mixed with a local oscillator signal (LO) in a direct conversion mixer. The communication signal, at certain times, will have both a communication signal of interest and interferor signals. The interferor signals induce signals in other portions of the mixer circuit, called interferor leakage signals, and the interaction between the two signals causes undesirable DC offsets in the mixer output. The DC offset compensator detects the presence of the interferor signals and provides a compensating signal to the output of the mixer such that the undesirable DC offset signals caused by the interferer self mixing and interferor interaction with even order-nonlinearities in the mixer are compensated out of the mixer output signal.

Abstract: A transmitter for a wireless handset having a modified translation loop architecture. The transmitter includes a VCO that generates a modulated transmit signal having a frequency fTx, and a modulated signal source that generates a modulated LO signal with a frequency fLO. A mixer mixes the transmit signal with the LO signal to produce an IF signal having a frequency fIF. A first divider divides the LO signal frequency fLO by an integer M to generate a first comparison signal having a frequency fCF. A second divider divides the IF signal frequency fIF, after it is multiplied by an integer K, by an integer N to generate a second comparison signal having a frequency fCF.

Abstract: Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator.

Abstract: Double balanced mixers having transistor pairs are affected by area mismatches between the transistors. The area mismatches can be represented as a ratio between the mixer core transistors that is directly related to voltage. Thus, an input voltage into one of the mixer core transistors in a transistor pair can compensate for the area mismatch. The compensation is achieved by a voltage track and hold feedback loop to one of the mixer core transistors.