Patents by Inventor Rahul Merwah

Rahul Merwah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware-assisted method for scheduling threads using data cache locality
    Patent number: 6938252
    Abstract: A method is provided for scheduling threads in a multi-processor system. In a first structure thread ids are stored for threads associated with a context switch. Each thread id identifies one thread. In a second structure entries are stored for groups of contiguous cache lines. Each entry is arranged such that a thread id in the first structure is capable of being associated with at least one contiguous cache line in at least one group, the thread identified by the thread id having accessed the at least one contiguous cache line. Patterns are mined for in the entries to locate multiples of a same thread id that repeat for at least two groups. Threads identified by the located multiples of the same thread id are mapped to at least one native thread, and are scheduled on the same processor with other threads associated with the at least two groups.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: August 30, 2005
    Assignee: International Business Machines Corporation
    Inventors: Sandra Johnson Baylor, Rahul Merwah
  • Hardware-assisted method for scheduling threads using data cache locality
    Publication number: 20020078124
    Abstract: A method is provided for scheduling threads in a multi-processor system. In a first structure thread ids are stored for threads associated with a context switch. Each thread id identifies one thread. In a second structure entries are stored for groups of contiguous cache lines. Each entry is arranged such that a thread id in the first structure is capable of being associated with at least one contiguous cache line in at least one group, the thread identified by the thread id having accessed the at least one contiguous cache line. Patterns are mined for in the entries to locate multiples of a same thread id that repeat for at least two groups. Threads identified by the located multiples of the same thread id are mapped to at least one native thread, and are scheduled on the same processor with other threads associated with the at least two groups.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 20, 2002
    Inventors: Sandra Johnson Baylor, Rahul Merwah