Patents by Inventor Rahul Nayak

Rahul Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9548104
    Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak
  • Publication number: 20170004874
    Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak
  • Patent number: 9105498
    Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Kota V. R. M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Patent number: 9070579
    Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 30, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Kota V. R. M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Patent number: 8954306
    Abstract: A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Junjun Li, Rahul Nayak
  • Publication number: 20150035075
    Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Mohit Bajaj, Kota V.R.M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Patent number: 8929039
    Abstract: Aspects of the invention provide for an electrostatic discharge (ESD) clamp. In one embodiment, the ESD clamp includes: a silicon controlled rectifier (SCR); and a trigger circuit for providing a tunable trigger voltage to turn on the SCR, the trigger circuit including a metal-insulator transition (MIT) material. The trigger circuit includes an MIT resistor that includes a width and a length that tunes the trigger voltage to a desired voltage.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mohit Bajaj, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Publication number: 20130314825
    Abstract: Aspects of the invention provide for an electrostatic discharge (ESD) clamp. In one embodiment, the ESD clamp includes: a silicon controlled rectifier (SCR); and a trigger circuit for providing a tunable trigger voltage to turn on the SCR, the trigger circuit including a metal-insulator transition (MIT) material. The trigger circuit includes an MIT resistor that includes a width and a length that tunes the trigger voltage to a desired voltage.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Publication number: 20130228872
    Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Kota V.R.M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
  • Patent number: 8489378
    Abstract: A model for a silicon controlled rectifier includes three diode models connected in series, with the middle diode model being reverse biased. Each diode model corresponds to and can be configured to simulate DC operation of a junction in the silicon controlled rectifier. The model can be used to evaluate behavior of a circuit that includes the silicon controlled rectifier. For example, the circuit can include an electrostatic discharge protection circuit that includes the silicon controlled rectifier.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Junjun Li, Rahul Nayak
  • Publication number: 20120004896
    Abstract: A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjun Li, Rahul Nayak
  • Publication number: 20110166847
    Abstract: A model for a silicon controlled rectifier includes three diode models connected in series, with the middle diode model being reverse biased. Each diode model corresponds to and can be configured to simulate DC operation of a junction in the silicon controlled rectifier. The model can be used to evaluate behavior of a circuit that includes the silicon controlled rectifier. For example, the circuit can include an electrostatic discharge protection circuit that includes the silicon controlled rectifier.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjun Li, Rahul Nayak