Patents by Inventor Rahul Nimaiyar
Rahul Nimaiyar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8933734Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: January 21, 2014Date of Patent: January 13, 2015Assignee: Achronix Semiconductor CorporationInventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Publication number: 20140201560Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: ApplicationFiled: January 21, 2014Publication date: July 17, 2014Applicant: Achronix Semiconductor CorporationInventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Patent number: 8638138Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: September 14, 2009Date of Patent: January 28, 2014Assignee: Achronix Semiconductor CorporationInventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Patent number: 8305124Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.Type: GrantFiled: December 2, 2011Date of Patent: November 6, 2012Assignee: Achronix Semiconductor CorporationInventors: Ravi Kurlagunda, Ravi Sunkavalli, Vijay Bantval, Rahul Nimaiyar
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Patent number: 8228101Abstract: Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed.Type: GrantFiled: September 14, 2009Date of Patent: July 24, 2012Assignee: Achronix Semiconductor CorporationInventors: Rahul Nimaiyar, Ravi Sunkavalli
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Publication number: 20120074991Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Inventors: Ravi Kurlagunda, Ravi Sunkavalli, Vijay Bantval, Rahul Nimaiyar
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Patent number: 8072250Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.Type: GrantFiled: September 14, 2009Date of Patent: December 6, 2011Assignee: Achronix Semiconductor CorporationInventors: Ravi Kurlagunda, Ravi Sunkavalli, Vijay Bantval, Rahul Nimaiyar
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Publication number: 20110063000Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: ApplicationFiled: September 14, 2009Publication date: March 17, 2011Inventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Publication number: 20110062999Abstract: Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed.Type: ApplicationFiled: September 14, 2009Publication date: March 17, 2011Inventors: Rahul Nimaiyar, Ravi Sunkavalli
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Publication number: 20110062997Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.Type: ApplicationFiled: September 14, 2009Publication date: March 17, 2011Inventors: Ravi Kurlagunda, Ravi Sunkavalli, Vijay Bantval, Rahul Nimaiyar
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Patent number: 6369619Abstract: The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage. The voltage tolerant input/output circuit includes (1) an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver is tri-stated, (2) a bias circuit logically configured to biased a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased, and (3) a driver circuit comprising the P-driver.Type: GrantFiled: July 14, 2000Date of Patent: April 9, 2002Assignee: Artisan Components, Inc.Inventors: Jamil Kawa, Rahul Nimaiyar, Puneet Sawhney, Anwar Awad