Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.

Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.

Abstract: A graphics processing pipeline may include at least two or more pipes, such that a lower frequency operation may be executed on one pipe while a higher frequency operation in the same instruction stream is executed at the same time on another pipe. In some cases, the lower frequency operation result may be held for later use in connection with the higher frequency operation on a different pipe. Especially where unused slots can be used for the lower frequency operation, efficiency may be improved.

Abstract: A shading rate may be set by analyzing samples within a pixel. Then based on that analysis, a system determines whether to use coarse pixel, pixel or sample shading for a region of pixels. Based on the determined type of shading, the shading rate may be set.

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Abstract: Instead of shading a triangle from the rasterizer as soon as it is known that there is a sample inside the triangle, in accordance with one embodiment, shading is delayed until the triangle beside it, called the neighboring triangle, is received. If there is a neighboring triangle facing the same way, with non-mutually exclusive coverage, meaning that it is not overlapping the same region, then the shader shades only once for the pair of triangles. That is, two separate fragments are merged and treated as one fragment. Specifically, the fragment that is over the pixel center is the one that is used and the other fragment is replaced by merging. The merger happens only over the extent of a pixel and more than one primitive is not shaded at a time. However, multiple merges within a 2×2 block of pixels are possible.

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.

Abstract: In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.

Abstract: In some embodiments, the intervals and the triangulation of an inner tessellation of a patch may be pre-computed. Even factor tessellations are arranged in a co-centric manner so that lower number factors are inside tessellations with higher number factors. Similarly, odd factor tessellations are arranged in a co-centric manner so that lower number factors are inside tessellations with higher number factors. Domain points of even factor tessellations are stored in a first table whereas domain points of odd factor tessellations are stored in a second table. At run time, the pre-computed values may be looked up for the applicable edge level of detail.

Abstract: Disclosed herein are approaches for detecting and/or generating silhouettes, in graphics processing applications, of objects (e.g., convex objects such as polyhedrons).

Abstract: In some embodiments, an edge cache data table for edges shared by two or more geometrically contiguous patches is generated. An identification value is assigned for each patch. When a first patch has a common edge with a second patch, a unique identification value is generated for an entry in the table based on identification values of the two patches with a common edge. Attributes of a common edge are stored in the entry in the table associated with the unique identification value. When the common edge is to be evaluated for the second patch, the edge can be read from the table in reverse order.

Abstract: A graphics processing pipeline may include at least two or more pipes, such that a lower frequency operation may be executed on one pipe while a higher frequency operation in the same instruction stream is executed at the same time on another pipe. In some cases, the lower frequency operation result may be held for later use in connection with the higher frequency operation on a different pipe. Especially where unused slots can be used for the lower frequency operation, efficiency may be improved.

Abstract: Apparatus, systems and methods for real-time, multi-resolution 3D collision detection using cube maps are disclosed. For example, a method is disclosed including receiving a first polygon, receiving a second polygon and then using a texture map stored in memory to detect collisions between the first and second polygons. Other implementations are also disclosed.

Abstract: In some embodiments, the intervals and the triangulation of an inner tessellation of a patch may be pre-computed. Even factor tessellations are arranged in a co-centric manner so that lower number factors are inside tessellations with higher number factors. Similarly, odd factor tessellations are arranged in a co-centric manner so that lower number factors are inside tessellations with higher number factors. Domain points of even factor tessellations are stored in a first table whereas domain points of odd factor tessellations are stored in a second table. At run time, the pre-computed values may be looked up for the applicable edge level of detail.

Abstract: In accordance with some embodiments, a tessellator may experience only a linear increase in tessellation time with increasing edge levels of detail. Conventionally, tessellators experience a non-linear or quadratic increase in tessellation time with increasing levels of detail. In some embodiments, the intervals and the triangulation of the inner tessellation may be pre-computed. Then at run time, the pre-computed values may be looked up for the applicable edge level of detail.

Abstract: Disclosed herein are approaches for detecting and/or generating silhouettes, in graphics processing applications, of objects (e.g., convex objects such as polyhedrons).

Abstract: A method is disclosed. The method includes receiving a first polygon, receiving a second polygon, determining a first distance corresponding to a distance from a first origin of the first polygon to a vertex of the second polygon, the origin of the first polygon and the vertex of the second polygon defining a direction vector, determining, along the direction vector a second distance corresponding to a distance from the first origin of the first polygon to a face of the first polygon; and detecting a collision between the first and second polygons if the second distance is greater than or equal to the first distance.