Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

Abstract: Methods and systems for optimizing signaling with traffic detection function are described herein. According to an implementation, a computing device, e.g., a session management function (SMF) in a wireless communication network, may receive, from a user plane function (UPF), a first message reporting detection of a first data flow from a user equipment. The computing device may configure a bearer to carry the first data flow based on a traffic flow template (TFT) and a quality of service (QoS) assigned by a policy control function (PCF). In some examples, the computing device may receive, from the UPF, a second message reporting detection of a second data flow from the user equipment. The computing device may update the TFT and use the QoS previously assigned to the bearer to carry the second data flow.

Abstract: On-package accelerators for integrating IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

Abstract: Systems and methods are provided for optimizing N10 interface messaging. Specifically, registration messages, de-registration messages, and the like can be dynamically controlled such that communication is prevented. Said messages are communicated via an N10 interface between a Unified Data Management function (UDM) and a Session Management function (SMF) in a 5G network. Additionally, subscription information, user profile information, etc., is also communicated via the N10 interface. Thus, the N10 interface can easily become overloaded or congested. Aspects herein provide mechanisms to avoid additional congestion of the N10 interface by intelligently eliminating specific messages communicated to the UDM via the N10 interface.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

Abstract: Methods and systems for optimizing signaling with traffic detection function are described herein. According to an implementation, a computing device, e.g., a session management function (SMF) in a wireless communication network, may receive, from a user plane function (UPF), a first message reporting detection of a first data flow from a user equipment. The computing device may configure a bearer to carry the first data flow based on a traffic flow template (TFT) and a quality of service (QOS) assigned by a policy control function (PCF). In some examples, the computing device may receive, from the UPF, a second message reporting detection of a second data flow from the user equipment. The computing device may update the TFT and use the QoS previously assigned to the bearer to carry the second data flow.

Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

Abstract: The disclosed system includes a first gateway of a first type configured to receive wireless packets from a core network node, and a second gateway of a second type colocated with the first gateway and configured to transmit at least a portion of the wireless packets to a network. The first gateway is configured with a first internet address that identifies the second gateway and a second internet address that identifies a third gateway of the second type. The first gateway is configured to transmit a first portion of the wireless packets to the second gateway based on the first internet address and transmit a second portion of the wireless packets to the third gateway based on the second internet address. The second gateway is configured with a third internet address that identifies the second gateway.

Abstract: In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

Abstract: Techniques for packet core network (PCN) gateway selection of collocated gateways are disclosed herein. A mobility management entity (MME) can retrieve charging characteristics (CC) information to determine whether collocated gateway selection is applicable for a UE. When collocated gateways are to be selected, the MME can configure domain name server (DNS) queries in a manner which is adapted for collocated gateway identification. Upon receipt of the DNS query, the DNS can be configured to identify collocated serving gateways (SGWs) which are each collocated with a packet gateway (PGW). The DNS can return identifications of the collocated SGWs to the MME, and the MME can use the identifications of the collocated SGWs to select a collocated SGW and a corresponding collocated PGW for use in connection with the network access for the user equipment.

Abstract: Described herein are techniques and systems for allocating Internet Protocol (IP) pools amongst user plane nodes in a distributed user plane architecture based on location information associated with the individual user plane nodes. In an example process, a control plane node of a telecommunication network receives, from a user plane node of the telecommunication network, location information during a packet forwarding control protocol (PFCP) association setup procedure, identifies, from a set of IP pools associated with the control plane node, an IP pool that is associated with matching location information that matches the location information received from the user plane node, and assigns the IP pool to the user plane node. By allocating IP pools in this manner, mobile-initiated scams, fraud, and/or cybersecurity attacks can be mitigated.

Abstract: Methods and systems for optimizing signaling with traffic detection function are described herein. According to an implementation, a computing device, e.g., a session management function (SMF) in a wireless communication network, may receive, from a user plane function (UPF), a first message reporting detection of a first data flow from a user equipment. The computing device may configure a bearer to carry the first data flow based on a traffic flow template (TFT) and a quality of service (QOS) assigned by a policy control function (PCF). In some examples, the computing device may receive, from the UPF, a second message reporting detection of a second data flow from the user equipment. The computing device may update the TFT and use the QoS previously assigned to the bearer to carry the second data flow.

Abstract: System and methods for efficient serving gateway and packet data gateway selections are described. A mobile device may attempt transmit an attach request to a network requesting packet data services in a particle protocol. A control plane of a serving gateway may receive the attach request and determine a serving gateway user plane that is configured to operate in the specified protocol. The serving gateway control plane may then propagate the determined serving gateway user plane to a packet data network gateway control plane for selection of the serving gateway user plane and a corresponding packet data network gateway user plane for use in providing packet services to the mobile device.

Abstract: A wireless communication network handles Session Management Function (SMF) outage in a Tracking Area (TA). An external SMF that is outside the TA registers with an internal Network Repository Function (NRF) that is inside in the TA. The internal NRF detects the SMF outage for an internal SMF inside the TA. The internal NRF receives an SMF request from an internal Access and Mobility Management Function (AMF) inside the TA. In response to the SMF outage, the internal NRF transfers an SMF response to the internal AMF that indicates the external SMF. The external SMF receives network signaling from the internal AMF and responsively directs an external User Plane Function (UPF) that is outside the TA to exchange user data with internal wireless access nodes that are inside the TA.

Abstract: In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.

Abstract: Solutions for providing a data traffic session for a user equipment (UE) over a wireless network comprises: receiving, by a session management node (e.g., a session management function, SMF), for a packet routing node (e.g., a user plane function, UPF), an indication of supported interne protocol (IP) traffic type (e.g., IPv4 or IPv6), wherein the indication of supported IP traffic type indicates support for a first IP traffic type or support for a second IP traffic type; allocating, by the session management node, to the packet routing node, a set of IP addresses based on at least the indication of supported IP traffic types, wherein allocating the set of IP addresses comprises allocating only supported IP addresses and withholding allocation of unsupported IP addresses; and providing, to the UE, using an IP address of the set of IP addresses, the data traffic session through the packet routing node.

Abstract: The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

Abstract: Techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. In various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (CMB). The target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. Communications via the CMB enable the target agent to determine, during a runtime of the network, whether a given initiator agent has been allocated an excessive number of credits, or an insufficient number of credits. In another embodiments, the target agent changes the distribution of credits to the initiator agents by allocating credits via the CMB.

Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

Abstract: A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.