Patents by Inventor Rahul Panat

Rahul Panat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10086432
    Abstract: Novel methods for micro-additive manufacturing three dimensional sub-millimeter components are disclosed herein. The methods can include dispensing a dielectric at positions on a substrate so as to provide dielectric structures having an aspect ratio of up to 1:20. The methods can also include in-situ curing of the dielectric structure upon dispensing of the dielectric wherein the dispensing and curing steps provide for three dimensional configurations. Direct printing a metal nanoparticle solution on the dielectric to create conductive traces and thereafter sintering the printed nanoparticle solution so as to cure the conductive traces enables three dimensional conductive (antenna) elements having a length and width scale of down to 1 ?m.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 2, 2018
    Assignee: WASHINGTON STATE UNIVERSITY
    Inventors: Rahul Panat, Deuk Hyoun Heo
  • Patent number: 9846276
    Abstract: A fiber grating device of low cost and arbitrary length is formed on a portion of a portion or the entirety of a highly elastic fiber optic core having a low Young's modulus of elasticity by causing elongation of the fiber optic core and forming or depositing a hard skin or cladding on the elongated fiber optic core. When the stress is then released, the hard skin or cladding buckles (including elastic or plastic deformation or both) to form wrinkles at the interface of the fiber optic core and the hard skin or cladding which are oriented circumferentially and highly uniform in height and spacing which can be varied at will by choice of materials, stretching, and thickness and composition of the cladding. Since the elastic elongation of the fiber optic core portion may be 200% or greater, an unprecedented measurement range is provided.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 19, 2017
    Assignee: Washington State University
    Inventors: Rahul Panat, Lei Li
  • Patent number: 9770759
    Abstract: Techniques for forming highly stretchable electronic interconnect devices are disclosed herein. In one embodiment, a method of fabricating an electronic interconnect device includes forming a layer of an adhesion material onto a surface of a substrate material capable of elastic and/or plastic deformation. The formed layer of the adhesion material has a plurality of adhesion material portions separated from one another on the surface of the substrate material. The method also includes depositing a layer of an interconnect material onto the formed layer of the adhesion material. The deposited interconnect material has regions that are not bonded or loosely bonded to corresponding regions of the substrate material, such that the interconnect material may be deformed more than the adhesion material attached to the substrate material. In certain embodiments, the interconnect material can also include a plurality of wrinkles on a surface facing away from the substrate material.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: September 26, 2017
    Assignee: Washington State University
    Inventors: Indranath Dutta, Rahul Panat
  • Patent number: 9627320
    Abstract: Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 18, 2017
    Assignee: INTEL CORPORATION
    Inventors: Rahul Panat, Bhanu Jaiswal
  • Publication number: 20160305771
    Abstract: A fiber grating device of low cost and arbitrary length is formed on a portion of a portion or the entirety of a highly elastic fiber optic core having a low Young's modulus of elasticity by causing elongation of the fiber optic core and forming or depositing a hard skin or cladding on the elongated fiber optic core. When the stress is then released, the hard skin or cladding buckles (including elastic or plastic deformation or both) to form wrinkles at the interface of the fiber optic core and the hard skin or cladding which are oriented circumferentially and highly uniform in height and spacing which can be varied at will by choice of materials, stretching, and thickness and composition of the cladding. Since the elastic elongation of the fiber optic core portion may be 200% or greater, an unprecedented measurement range is provided.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 20, 2016
    Applicant: Washington State University
    Inventors: Rahul Panat, Lei Li
  • Publication number: 20160172741
    Abstract: Novel methods for micro-additive manufacturing three dimensional sub-millimeter components are disclosed herein. The methods can include dispensing a dielectric at positions on a substrate so as to provide dielectric structures having an aspect ratio of up to 1:20. The methods can also include in-situ curing of the dielectric structure upon dispensing of the dielectric wherein the dispensing and curing steps provide for three dimensional configurations. Direct printing a metal nanoparticle solution on the dielectric to create conductive traces and thereafter sintering the printed nanoparticle solution so as to cure the conductive traces enables three dimensional conductive (antenna) elements having a length and width scale of down to 1 ?m.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 16, 2016
    Applicant: Washington State University
    Inventors: Rahul Panat, Deuk Hyoun Heo
  • Publication number: 20160167132
    Abstract: Techniques for additive deposition are disclosed herein. In one embodiment, a method includes depositing a first portion of a precursor material onto a deposition platform, the precursor material including a suspension of nano-particles and forming a first solid structure of the nano-particles on the deposition platform from the deposited first layer of the precursor material. The method can also include depositing a second portion of the precursor material onto the formed first solid structure of the nano-particles and forming a second solid structure on the first solid structure from the deposited second layer of the precursor material. The three dimensional structure thus formed can be partly or fully cured or sintered during deposition or after deposition resulting in a controlled hierarchical porosity at multiple levels, from mesoscale (e.g., about 10 ?m to about 250 ?m) to nanoscale (e.g., about 900 nm or less) in the same structure.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 16, 2016
    Inventor: Rahul Panat
  • Publication number: 20160170447
    Abstract: Techniques for forming highly stretchable electronic interconnect devices are disclosed herein. In one embodiment, a method of fabricating an electronic interconnect device includes forming a layer of an adhesion material onto a surface of a substrate material capable of elastic and/or plastic deformation. The formed layer of the adhesion material has a plurality of adhesion material portions separated from one another on the surface of the substrate material. The method also includes depositing a layer of an interconnect material onto the formed layer of the adhesion material. The deposited interconnect material has regions that are not bonded or loosely bonded to corresponding regions of the substrate material, such that the interconnect material may be deformed more than the adhesion material attached to the substrate material. In certain embodiments, the interconnect material can also include a plurality of wrinkles on a surface facing away from the substrate material.
    Type: Application
    Filed: August 29, 2015
    Publication date: June 16, 2016
    Inventors: lndranath Dutta, Rahul Panat
  • Publication number: 20150048508
    Abstract: Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2011
    Publication date: February 19, 2015
    Inventors: Rahul Panat, Bhanu Jaiswal
  • Patent number: 8724290
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Rahul Panat
  • Publication number: 20120050940
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 1, 2012
    Inventors: Nachiket Raravikar, Rahul Panat
  • Patent number: 8068328
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Rahul Panat
  • Publication number: 20090231777
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 17, 2009
    Inventors: Nachiket R. Raravikar, Rahul Panat