Abstract: A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift layer having a first conductivity type, a JFET region that has the first conductivity type in the upper portion of the drift layer, a plurality of well regions having a second conductivity type in an upper portion of the drift layer, each well region forming a respective island within the JFET region when viewed in plan view, and a plurality of source regions having the first conductivity type, where each source region is within a respective one of the well regions. The JFET region comprises a plurality of spaced-apart first JFET sub-regions that each has a first doping concentration and a second JFET sub-region that has a second doping concentration that is lower than the first doping concentration, the second JFET region extending around at least one of the first JFET sub-regions when viewed in plan view.

Abstract: A method of forming a semiconductor device includes forming mesa stripe structure on a semiconductor substrate, the mesa stripe structure including a plurality of alternating trenches and mesa stripes, forming a dielectric spacer on the mesa stripe structure, and forming an etch mask on a portion of the mesa stripe structure. The etch mask covers at least a portion of a first mesa stripe of the plurality of mesa stripes. The dielectric spacer is etched to expose surfaces of the mesa stripes other than the portion of the first mesa stripe that is covered by the etch mask. The etch mask is removed, and a metal layer is formed on the mesa stripe structure. The metal layer forms metal contacts to the exposed surfaces of the mesa stripes. Related semiconductor devices are also disclosed.

Abstract: A semiconductor device includes a substrate and an epitaxial structure on the substrate. The epitaxial structure includes a drift region and a mesa stripe on the drift region. The mesa stripe includes a channel region on the drift region, a source region on the channel region, and sidewall gate regions on opposite sides of the channel region. The channel region and the source region have a first conductivity type and the sidewall gate regions have a second conductivity type opposite the first conductivity type. The drift region includes a central pillar having the first conductivity type and outer pillars on opposite sides of the central pillar. The outer pillars have the first conductivity type, and the outer pillars and the central pillar form a superjunction structure in the drift region. Related methods are also disclosed.

Abstract: A method of forming a semiconductor device includes providing a first layer including silicon carbide having a first conductivity type, and forming a plurality of doped regions having a second conductivity type in the silicon carbide layer. A second layer including nickel is provided on the first layer and contacts the plurality of doped regions and the first layer. The first layer and the second layer are annealed at a first anneal temperature to form a layer of nickel silicide on the first layer. The first layer and the layer of nickel silicide are annealed at a second anneal temperature that is greater than first anneal temperature to cause the layer of nickel silicide to form ohmic junctions to the plurality of doped regions and to form a Schottky barrier junction to the first layer.

Abstract: A Schottky diode according to some embodiments includes a silicon carbide drift layer having a first conductivity type, and a junction shielding region in the drift layer. The junction shielding region has a second conductivity type opposite the first conductivity type. The Schottky diode further includes an anode contact on the silicon carbide drift layer. The anode contact includes a refractory metal nitride, and forms a Schottky junction with the drift layer and an ohmic contact to the junction shielding region.

Abstract: A semiconductor device includes a semiconductor layer having a first area and an edge termination area outside the first area. The semiconductor layer has a first conductivity type, an active area in the first area, a test area in the first area adjacent the active area, a first anode contact on the semiconductor layer in the active area, a second anode contact on the semiconductor layer in the test area, and a cathode contact in electrical contact with the semiconductor layer. A related method of testing surge current capability of a semiconductor device includes applying a forward current that is smaller than a maximum forward current of the semiconductor device to a test active area that is within an area inside a main edge termination area of the semiconductor device, and detecting a failure of the semiconductor device in response to the forward current.

Abstract: A semiconductor device includes a semiconductor layer including an active area, a first implanted region within the active area at a surface of the semiconductor layer, and an integrated test area in the semiconductor layer. The integrated test area includes a second implanted region in the semiconductor layer.

Abstract: A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.

Abstract: A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that extend in the first direction and mesa surfaces at opposite ends of the mesa stripes. An additional mesa region is formed at an end of at least one of the mesa stripes. The additional mesa region is electrically insulated from the at least one of the mesa stripes. A semiconductor device structure includes a plurality of mesa stripes that extend in a first direction and include mesa sidewalls that extend in the first direction and mesa end surfaces at opposite ends of the mesa stripes. An additional mesa region that is electrically insulated from the at least one of the mesa stripes is at an end of at least one of the mesa stripes.

Abstract: A semiconductor device includes a semiconductor layer having an active region and an edge termination region, and first metal regions on the semiconductor layer in the active region of the semiconductor layer. The first metal regions include a first metal. The device further includes second metal regions on the semiconductor layer in the edge termination region of the semiconductor layer. The second metal regions include the first metal. The device includes a first metal layer on the semiconductor layer in the active region of the semiconductor layer. The first metal layer includes a second metal, and the metal layer contacts the first metal regions and contacts the semiconductor layer in spaces between the first metal regions.

Abstract: Transistors are provided that comprise a silicon carbide based semiconductor layer structure, a first current terminal, a second current terminal, a gate terminal, and a minimum gate terminal-to-second current terminal voltage clamp circuit in the semiconductor layer structure that is coupled between the gate terminal and the second current terminal.

Abstract: A method of forming a buried implanted region in a silicon carbide semiconductor layer includes implanting first dopant ions into the silicon carbide semiconductor layer at a first dose and first implant energy to form a first channelized doping profile having a first de-channeled peak at a first depth in the silicon carbide semiconductor layer and a first channeled peak at a second depth that is greater than the first depth. Second dopant ions are implanted into the silicon carbide semiconductor layer at a second dose and second implant energy to form a second channelized doping profile. The second channelized doping profile has a second channeled peak at a third depth in the silicon carbide semiconductor layer that is between the first depth and the second depth. The first channelized doping profile and the second channelized doping profile form a combined doping profile that defines the buried implanted region.

Abstract: Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Abstract: A power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region and a gate region in the mesa adjacent the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration that is greater than the first doping concentration.

Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.

Abstract: A Junction Barrier Schottky (JBS) diode includes an N-type epitaxial layer disposed on SiC substrate, P+ wavy regions are disposed in the epitaxial layer adjoining a top planar surface, each of which is separated from an adjacent one of the wavy regions by a Schottky barrier contact region. P+ island regions are disposed in the Schottky barrier contact regions. A top metal layer is disposed along the top planar surface in direct contact with the Schottky barrier contact regions, the P+ wavy regions, and the P+ island regions, the top metal layer comprising the anode of the JBS diode. A bottom metal layer is disposed beneath the SiC substrate. The bottom metal layer comprises the cathode of the JBS diode.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.