Patents by Inventor Rahul S. Jain

Rahul S. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862552
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Publication number: 20220130748
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Applicant: INTEL CORPORATION
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Patent number: 11251113
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Publication number: 20190198436
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li