Patents by Inventor Rahul Sarpeshkar

Rahul Sarpeshkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040056696
    Abstract: An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.
    Type: Application
    Filed: July 8, 2003
    Publication date: March 25, 2004
    Applicant: Agere Systems Inc.
    Inventors: Ruben Herrera, Rahul Sarpeshkar
  • Publication number: 20030218118
    Abstract: An optical transient sensor circuit includes a photodiode in series with a MOS feedback transistor connected across a voltage difference. An inverting amplifier having its input connected to the common connection between the photodiode and the MOS feedback transistor and its output connected to an output-node for a measure of the incoming irradiance. A charge/discharge circuit, having an input connected to the output of the inverting amplifier, having an output connected to the gate of the MOS feedback transistor and having a first and second output for half-wave rectified and thresholded contrast encoding measures of positive and negative irradiance transients. A capacitor connected between a constant potential and the gate of the MOS feedback transistor.
    Type: Application
    Filed: May 23, 2002
    Publication date: November 27, 2003
    Inventors: Jorg Kramer, Rahul Sarpeshkar
  • Patent number: 6621319
    Abstract: An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 16, 2003
    Assignee: Agere Systems Inc.
    Inventors: Ruben Herrera, Rahul Sarpeshkar
  • Publication number: 20020195644
    Abstract: An apparatus having a circuit coupled to the gate contact of a field effect transistor wherein the transistor's gate includes a dielectric layer of which at least a portion is an organic dielectric. The circuit is configured to produce one or more storage voltage pulses that cause charge to be stored in the gate. The field effect transistor has a semiconductor layer with a conductive path whose conductivity changes for a given Vg in response to storing the charge. The circuit may produce one or more dissipation voltage pulses having a voltage of opposite sign to the one or more storage pulses, that cause dissipation of charge stored in the gate. Further disclosed are a memory and a method of electronically storing and reading information, both utilizing the organic-based polarizable gate transistor apparatus.
    Type: Application
    Filed: June 8, 2001
    Publication date: December 26, 2002
    Inventors: Ananth Dodabalapur, Howard E. Katz, Rahul Sarpeshkar
  • Patent number: 6484559
    Abstract: A circuit includes at least one odor-sensitive organic field effect transistor (OFET) having a conduction channel whose conductivity changes in response to certain ambient odors and a feedback loop coupled between an output and an input of the circuit. The feedback loop generates a feedback signal which stabilizes the output signal of the circuit for time drift of the odor-sensitive organic transistor. In one embodiment, the OFET is an integral part of an amplifier and generates input signals to the amplifier in response to certain odors. A selectively enabled switch may be coupled between the output and the input of the amplifier circuit to provide negative feedback that tends to cancel the effect on the amplifier of time drift due to the OFET.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: November 26, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Ananth Dodabalapur, Rahul Sarpeshkar
  • Publication number: 20020116982
    Abstract: A circuit includes at least one odor-sensitive organic field effect transistor (OFET) having a conduction channel whose conductivity changes in response to certain ambient odors and a feedback loop coupled between an output and an input of the circuit. The feedback loop generates a feedback signal which stabilizes the output signal of the circuit for time drift of the odor-sensitive organic transistor. In one embodiment, the OFET is an integral part of an amplifier and generates input signals to the amplifier in response to certain odors. A selectively enabled switch may be coupled between the output and the input of the amplifier circuit to provide negative feedback that tends to cancel the effect on the amplifier of time drift due to the OFET.
    Type: Application
    Filed: February 26, 2001
    Publication date: August 29, 2002
    Inventors: Ananth Dodabalapur, Rahul Sarpeshkar
  • Patent number: 6384804
    Abstract: A display apparatus according to our invention comprises a multiplicity of nominally identical smart pixels, a given pixel comprising an organic light emitting diode and an organic or inorganic (e.g., amorphous or polycrystalline Si) pixel FET. The display also comprises drive/compensation circuitry adapted for mitigating or eliminating non-idealities associated with the organic components. Among the non-idealities are variations in mobility and/or threshold voltage of the pixel FET from transistor to transistor, change in mobility and/or threshold voltage with time in a given pixel FET, change over time of the LED characteristics, capacitive signal feed-through through the gate insulator of the pixel FETs by short rise/fall time pulses, poor on-off ratio of the pixel FET, and charge leakage through the gate dielectric. Exemplary drive/compensation circuitry is disclosed.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: May 7, 2002
    Assignee: Lucent Techonologies Inc.
    Inventors: Ananth Dodabalapur, Rahul Sarpeshkar
  • Patent number: 6377194
    Abstract: An analog computation system which forms a hybrid between analog and digital computation. The analog signal is divided into a plurality of separated analog signals, each of the different analog signals collectively representing the original analog signal, and each having less resolution then the total desired resolution. A number of different analog computation elements carry out a mathematical function on the separated signal. Different stages may be provided, and a signal restoration device may be provided between the different stages.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: April 23, 2002
    Assignee: California Institute of Technology
    Inventor: Rahul Sarpeshkar
  • Patent number: 6292023
    Abstract: A finite state machine in which n discrete states of the machine are encoded using a set of n bistable elements permitting simplified decoding of states. Transitions between discrete states are illustratively executed by selectively directing a bistable device to a 1 state using transition circuits activated by positive transitions of asynchronous spiking inputs. In one illustrative embodiment the positive transition is capacitively coupled to a switch that connects the complement output of a bistable element to ground, thereby causing the nominal output of that element to approach a voltage corresponding to a 1 state. In a second illustrative embodiment a pass transistor combination maintains a capacitor at the nominal output voltage of the bistable element in a 1 state until a spiking input signal arrives. A combination of the spiking input signal and the voltage on the capacitor connects the complement output of another bistable element to ground, thus switching that other bistable element.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 18, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Ruben Herrera, Rahul Sarpeshkar
  • Patent number: 6262678
    Abstract: A/D conversion of a current input is performed with integrate-and-fire spiking neurons. Techniques that upcount or downcount the number of spikes fired by one neuron in a time period established by another neuron yield quantized estimates of analog charge residues created by the input current. Recursive application of alternate upcounting and downcounting operations yields successively finer quantization estimates that are terminated by an error-correction operation to obtain the least significant bit of the conversion. A spike-based hybrid state machine (HSM) employing both analog and digital elements is configured to create a 2-step or a successive-subranging analog-to-digital converter. The speed of the conversion is augmented in a pipelined topology. In the HSM, a spike-triggered finite state machine (FSM) controls the input currents to the spiking neurons and is in turn controlled by spikes arising from these neurons.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: July 17, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: Rahul Sarpeshkar
  • Patent number: 6242988
    Abstract: A spiking neuron circuit providing a spiking output signal in response to an input current that causes a first capacitor to charge to a threshold voltage. In response to achieving such threshold, an output terminal is connected to a voltage, illustratively VDD, for a period determined by an applied voltage, Vpw. Rapid switching of the output to its spiking level is achieved using a positive feedback path, and deactivation of such feedback rapidly terminates the spiking period.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: June 5, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: Rahul Sarpeshkar
  • Patent number: 6212289
    Abstract: An integrated circuit that computes the velocity of a visual stimulus moving between two photoreceptor locations is disclosed. In its most basic version, the circuit comprises two temporal edge detectors with photoreceptors, two pulse-shaping circuits, and one motion circuit on a single silicon chip. Velocity is computed from the signed time delay of the appearance of an image feature at the two photoreceptor locations. Specifically, each temporal edge detector de tects a rapid irradiance transient at its photoreceptor location and converts it into a short current spike. This current spike is transformed into two different voltage pulses, a fast pulse and a slowly-decaying pulse, by the pulse-shaping circuit that is coupled to the temporal edge detector.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: April 3, 2001
    Assignee: California Instititute of Technology
    Inventors: Rahul Sarpeshkar, Jörg Kramer, Christof Koch
  • Patent number: 6212288
    Abstract: An integrated circuit that computes the velocity of a visual stimulus moving between two photoreceptor locations is disclosed. In its most basic version, the circuit comprises two temporal edge detectors with photoreceptors, two pulse-shaping circuits, and one motion circuit on a single silicon chip. Velocity is computed from the signed time delay of the appearance of an image feature at the two photoreceptor locations. Specifically, each temporal edge detector detects a rapid irradiance transient at its photoreceptor location and converts it into a short current spike. This current spike is transformed into two different voltage pulses, a fast pulse and a slowly-decaying pulse, by the pulse-shaping circuit that is coupled to the temporal edge detector.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: April 3, 2001
    Assignee: California Institute of Technology
    Inventors: Rahul Sarpeshkar, Jörg Kramer, Christof Koch
  • Patent number: 6088467
    Abstract: An integrated circuit that computes the velocity of a visual stimulus moving between two photoreceptor locations is disclosed. In its most basic version, the circuit comprises two temporal edge detectors with photoreceptors, two pulse-shaping circuits, and one motion circuit on a single silicon chip. Velocity is computed from the signed time delay of the appearance of an image feature at the two photoreceptor locations. Specifically, each temporal edge detector detects a rapid irradiance transient at its photoreceptor location and converts it into a short current spike. This current spike is transformed into two different voltage pulses, a fast pulse and a slowly-decaying pulse, by the pulse-shaping circuit that is coupled to the temporal edge detector.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: July 11, 2000
    Assignee: California Institute of Technology
    Inventors: Rahul Sarpeshkar, Jorg Kramer, Christof Koch
  • Patent number: 6023521
    Abstract: An integrated circuit that computes the velocity of a visual stimulus moving between two photoreceptor locations is disclosed. In its most basic version, the circuit comprises two temporal edge detectors with photoreceptors, two pulse-shaping circuits, and one motion circuit on a single silicon chip. Velocity is computed from the signed time delay of the appearance of an image feature at the two photoreceptor locations. Specifically, each temporal edge detector detects a rapid irradiance transient at its photoreceptor location and converts it into a short current spike. This current spike is transformed into two different voltage pulses, a fast pulse and a slowly-decaying pulse, by the pulse-shaping circuit that is coupled to the temporal edge detector.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: February 8, 2000
    Assignee: California Institute of Technology
    Inventors: Rahul Sarpeshkar, Jorg Kramer, Christof Koch
  • Patent number: 5781648
    Abstract: An integrated circuit that computes the velocity of a visual stimulus moving between two photoreceptor locations is disclosed. In its most basic version, the circuit comprises two temporal edge detectors with photoreceptors, two pulse-shaping circuits, and one motion circuit on a single silicon chip. Velocity is computed from the signed time delay of the appearance of an image feature at the two photoreceptor locations. Specifically, each temporal edge detector detects a rapid irradiance transient at its photoreceptor location and converts it into a short current spike. This current spike is transformed into two different voltage pulses, a fast pulse and a slowly-decaying pulse, by the pulse-shaping circuit that is coupled to the temporal edge detector.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: July 14, 1998
    Assignee: California Institute of Technology
    Inventors: Rahul Sarpeshkar, Jorg Kramer, Christof Koch
  • Patent number: 5463348
    Abstract: A novel family of CMOS differential and transconductance amplifiers has wide input linear range and is suited for low power operation. The wide linear range is obtained by "widening the tanh", or decreasing the ratio of transconductance to bias current, by combining the three techniques of (a) using the well terminals of the input differential-pair transistors as the amplifier inputs; (b) using the feedback technique known as source degeneration; and (c) using the novel feedback technique of gate degeneration. According to one preferred embodiment of the present invention a compact transconductance amplifier having a linear range of .+-.1 V was achieved in an 11-transistor circuit with a DC-input operating range of 1 V-5 V in a low-power subthreshold CMOS technology in a standard 2 micron process.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: October 31, 1995
    Assignee: California Institute of Technology
    Inventors: Rahul Sarpeshkar, Carver A. Mead