Abstract: The present invention relates to the design of the Antisense-oligonucleotide complementary to the specific region of peptide deformylase gene from Mycobacterium tuberculosis. The use of this Antisense-oligonucleotide on mycobacterial culture inhibits the production of the peptide deformylase enzyme by hybridizing within the region, which is found to be responsible for maintaining stability as well as retaining the functionality of the enzyme and thus in turn affecting the growth of the cells. This invention also establishes the essentiality of the peptide deformylase enzyme in mycobacteria and claims it as a drug target in this microorganism.

Abstract: A switch and a process of operating a switch are described where a received data frame is copied one or more times into a memory before being transmitted out of the switch. The switch and method determine how much space in the memory is needed to store all of the copies of the received data frame and then the switch and method determine locations in the memory for storing the copies of the received data frames. The copies of the received data frame are stored until the ports designated as transmitting the copies of the received data frame are ready. When a port is ready, a copy of the received data frame is read out of the memory and the port is instructed where to locate the copy on a bus. When the port has retrieved the copy of the data frame, it transmits the data frame out of the switch.

Abstract: The present invention relates to the design of the Antisense-oligonucleotide complementary to the specific region of peptide deformylase gene from Mycobacterium tuberculosis. The use of this Antisense-oligonucleotide on mycobacterial culture inhibits the production of the peptide deformylase enzyme by hybridizing within the region, which is found to be responsible for maintaining stability as well as retaining the functionality of the enzyme and thus in turn affecting the growth of the cells. This invention also establishes the essentiality of the peptide deformylase enzyme in mycobacteria and claims it as a drug target in this microorganism.

Abstract: A switch and a process of operating a switch are described where a received data frame is copied one or more times into a memory before being transmitted out of the switch. The switch and method determine how much space in the memory is needed to store all of the copies of the received data frame and then the switch and method determine locations in the memory for storing the copies of the received data frames. The copies of the received data frame are stored until the ports designated as transmitting the copies of the received data frame are ready. When a port is ready, a copy of the received data frame is read out of the memory and the port is instructed where to locate the copy on a bus. When the port has retrieved the copy of the data frame, it transmits the data frame out of the switch.

Abstract: A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is congestion of resources within the system and transfers data packets to external memory to ease the congestion. Data packets are eventually transferred from the internal or external memory to one or more output ports.

Abstract: A system for facilitating the reorganization of the information technology of a business organization into a structure that is modular and, thus, interchangeable between business units within the enterprise, and particularly within World Wide Web enterprises involving several correlated companies. A computer controlled system is provided for modularizing the information technology structure of a business organization into a structure of interchangeable holonic self-contained modules, with each module performing a set of related functions comprising means for providing a plurality of sets of self-controlling holons, with each holon in each set performing a business capability of the same type as performed by the other holons in its respective set but each set of holons performing a different business capability type than the other sets of holons.

Abstract: A video decoder cache used for motion compensation data may be dynamically reconfigured. In some embodiments, it may be reconfigured on picture or frame boundaries and in other embodiments it can be reconfigured on sequence boundaries. The cache may be flushed on each boundary to enable such reconfiguration.

Abstract: A switch and a process of operating a switch are described where a received data frame is stored into memory in a systematic way. In other words, a location is selected in the memory to store the received data frame using a non-random method. By storing the received data frame in this way, switches that employ this system and method increase bandwidth by avoiding delays incurred in randomly guessing at vacant spaces in the memory. The received data frame is stored until a port that is to transmit the received data frame is available. Throughput is further improved by allowing the received data frames to be stored in either contiguous or non-contiguous memory locations.

Abstract: Systems and methods are disclosed for capturing data representative of user interactions with a desktop computer, and processing the capture data to identify and analyze business processes performed by the user. The disclosed system comprises listeners that capture key actuations, mouse-clicks, screen information, and other data representative of user interaction with a desktop computer. A desktop observer is provided to accept capture data from listeners, to temporarily store the capture data if necessary, and to pass the capture data to a process intelligence server. The process intelligence server includes a process discovery module the analyzes the capture data and identifies business processes corresponding to the capture data, or models business processes. A process data master storage is provided.

Abstract: According to some embodiments, a first value of a first parameter type is received in connection with a macroblock that represents a portion of an image. The macroblock may be divided into a first set of sub-portions, and different values of the first parameter type may be associated with different sub-portions of the first set. The first value may then be stored in a context buffer that includes a first context area associated with the first parameter type and a second context area associated with a second parameter type. The first context area might be, for example, adapted to store fewer values for each parameter type as compared to the second context area.

Abstract: According to some embodiments, an external memory unit stores rows of macroblocks representing an image. A set of macroblocks may be transferred from the external memory unit to a local buffer, the set of macroblocks including fewer macroblocks than a row. A macroblock may then be decoded based on information in the local buffer to generate an image signal.

Abstract: The invention discloses an improved process for producing 4-(1H-1,2,4-triazol-1-ylmethyl)benzonitrile of Formula (Structure 2), an intermediate used in the manufacture of 4,4?-[1H-1,2,4-triazol-1-ylmethylene] bisbenzonitrile (Letrozole), the process comprising of reacting salt of 1,2,4-triazole of Formula (Structure 4) with ?-halo substituted tolunitrile of Formula (Structure 3) in presence of dimethylformamide, wherein the X represents alkali metals selected from a group of Li, Na, or K, preferably Na and Y represents a halogen group selected from Cl, Br or I, preferably Br.

Abstract: Systems and methods for IP multicast packet burst absorption and multithreaded replication architecture are disclosed. Replications of IP multicast packets are performed in a control plane of a network device. The network device may include a data plane for transmitting data between ingress and egress ports and a control plane including a shared transmit/receive queue infrastructure configured to queue incoming multicast packets to be replicated on a per ingress port basis and to queue transmit packets, and a multicast processing engine in communication with the shared queue infrastructure and including a circular replication buffer to facilitate multithreaded replication of multicast packets on a per egress virtual local area network (VLAN) replication basis. The shared transmit/receive queue infrastructure may dynamically allocate memory between the transmit and receive multicast queues.

Abstract: Systems and methods for committed access rate (CAR) system architecture in an IP/Ethernet network with optional dynamic packet memory reservation are disclosed. The method includes classifying each received packet into a quality of service (QoS) group using the packet header information, defining a traffic transmission rate profile such as by using a token bucket model to measure and check the traffic rate profile of the incoming packet against a corresponding service level agreement (SLA), marking the packet as in profile or out of profile, and performing packet buffer memory reservation to guarantee memory space for in profile CAR packets. Buffer memory reservation may be via static or dynamic memory reservation. Dynamic memory reservation eliminates the need for hard boundaries to restrict non-CAR packets. A push-out (e.g., head-drop) mechanism may be employed to push out non-CAR packets when the network traffic is congested.

Abstract: Numerous embodiments of a method of operating a network switch are disclosed. In one embodiment, such a method comprises receiving electronic data on a first port of a data networking device, deleting at least a portion of the electronic data prior to providing the electronic data to the memory of the data networking device, and modifying the electronic data prior to providing at least a portion of the electronic data to a second port.

Abstract: A method and apparatus for replacing a CRC with a reduced size data integrity indication is disclosed. In one embodiment, a shared memory ethernet switch includes logic to replace a 4-byte CRC field of a frame with a 1 byte CRC prior to storing the frame in shared memory. Upon reading the frame from memory, the 1 byte CRC is used for error checking.

Abstract: A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is congestion of resources within the system and transfers data packets to external memory to ease the congestion. Data packets are eventually transferred from the internal or external memory to one or more output ports.

Abstract: A method and system is provided for synchronizing multi-level memory. The system has an internal memory and an external memory. Data packets are initially stored in the internal memory. A determination is made as to whether to transfer the data packet to the external memory based on congestion of system resources. When it is time to transfer a data packet that should be stored in external memory to an output port, a determination is made as to whether the data packet has actually been transferred to the external memory. If the data packet has been transferred to the external memory, the data packet is retrieved from the external memory and transferred to the output port. Otherwise, no attempt is made to transfer the data packet from external memory to the output port until the data packet has been transferred to the external memory. This ensures that no attempt is made to retrieve the data packet from the external memory when the data packet is still being stored in the internal memory.

Abstract: A system for facilitating the reorganization of the information technology of a business organization into a structure that is modular and, thus, interchangeable between business units within the enterprise, and particularly within World Wide Web enterprises involving several correlated companies.

Abstract: A switch and a process of operating a switch are described where a received data frame is stored into memory in a systematic way. In other words, a location is selected in the memory to store the received data frame using a non-random method. By storing the received data frame in this way, switches that employ this system and method increase bandwidth by avoiding delays incurred in randomly guessing at vacant spaces in the memory. The received data frame is stored until a port that is to transmit the received data frame is available. Throughput is further improved by allowing the received data frames to be stored in either contiguous or non-contiguous memory locations.