Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: A burst-mode TIA circuit for use in PON receivers is provided that supports multiple data rates, has high receiver sensitivity, wide dynamic range, and that performs burst-mode synchronization very quickly. The multi-rate burst-mode TIA circuit has a high-speed data path that has low input-referred noise. Based on the chosen data rate at which the multi-rate burst-mode TIA circuit will operate, the rate select switch selects an appropriate feedback resistor of the resistive feedback network.

Abstract: A burst-mode TIA circuit for use in PON receivers is provided that supports multiple data rates, has high receiver sensitivity, wide dynamic range, and that performs burst-mode synchronization very quickly. The multi-rate burst-mode TIA circuit has a high-speed data path that has low input-referred noise. Based on the chosen data rate at which the multi-rate burst-mode TIA circuit will operate, the rate select switch selects an appropriate feedback resistor of the resistive feedback network.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a single-to-differential variable gain amplifier having a variable resistor switch that substantially always operates in a triode region at all time. Said another way, the resistor switch is configured to operate in a triode region regardless of whether or not a first portion of an input signal to the variable gain amplifier is larger than a second portion of the input signal. The disclosed scheme helps to keep the variable resistor switch in the triode region in all cases of operation, thereby maintaining the linearity condition and reducing distortion in the variable gain amplifier.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a single-to-differential variable gain amplifier having a variable resistor switch that substantially always operates in a triode region at all time. Said another way, the resistor switch is configured to operate in a triode region regardless of whether or not a first portion of an input signal to the variable gain amplifier is larger than a second portion of the input signal. The disclosed scheme helps to keep the variable resistor switch in the triode region in all cases of operation, thereby maintaining the linearity condition and reducing distortion in the variable gain amplifier.

Abstract: An optical communication system, a circuit, and a method of operating an optical communication system are provided. The optical communication system is disclosed to include a photodiode configured to receive optical signals and convert the received optical signals into electrical signals, a Trans-Impedance Amplifier (TIA) electrically connected with the photodiode such that the TIA receives the electrical signals from the photodiode and is configured to convert the electrical signals received from the photodiode into amplified electrical signals, and a feedback loop connected between an input of the TIA and an output of the TIA that includes a switchable capacitor bank connected thereto which introduces at least one zero into a feedback factor transfer function of the TIA thereby tuning out poles or equalizing delay introduced by a TIA input network connected between the photodiode and the input of the TIA.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: Disclosed is a method and system for generic object detection using block-based feature computation and, more specifically, a method and system for massively parallel computation of object features sets according to an optimized clock-cycle matrix. The method uses an array of correlators to calculate block sums for each section of the image to be analyzed. A greedy heuristic scheduling algorithm is executed to produce an optimized clock cycle matrix such that overlapping features which use the same block sum do not attempt to access the block at the same time, thereby avoiding race memory conditions. The processing system can employ any of a variety of hardwired Very Large Scale Integration (VLSI) chips such as Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs).

Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Abstract: Disclosed is a method and system for generic object detection using block-based feature computation and, more specifically, a method and system for massively parallel computation of object features sets according to an optimized clock-cycle matrix. The method uses an array of correlators to calculate block sums for each section of the image to be analyzed. A greedy heuristic scheduling algorithm is executed to produce an optimized clock cycle matrix such that overlapping features which use the same block sum do not attempt to access the block at the same time, thereby avoiding race memory conditions. The processing system can employ any of a variety of hardwired Very Large Scale Integration (VLSI) chips such as Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs).

Abstract: Circuits, demultiplexers, and methods are disclosed. A circuit includes a reference clock input to receive clock pulses at a reference clock speed. An internal divided clock input receives a divided clock signal from a clock divider that is driven by the clock pulses. The clock divider generates the divided clock signal at a second clock speed that is a fraction of the reference clock speed. An external divided clock input receives an external divided clock signal. The external divided clock signal is driven by the clock pulses and operates at the second clock speed. A clock transition synchronization circuit suppresses application of one or more of the clock pulses to the clock divider when the divided clock signal transitions between clock states out of synchronization with the external divided clock signal.

Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.