Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: The present invention relates to a method for manufacturing a plurality of nanostructures comprising the steps of providing a plurality of protruding base structures (104) arranged on a surface of a first substrate (102), providing a seed layer mixture, comprising a solvent/dispersant and a seed material, in contact with the protruding base structures, providing a second substrate arranged in parallel with the first substrate adjacent to the protruding base structures, thereby enclosing a majority of the seed layer mixture between the first and second substrates, evaporating the solvent, thereby forming a seed layer (110) comprising the seed material on the protruding base structures, removing the second substrate, providing a growth mixture, comprising a growth agent, in contact with the seed layer, and controlling the temperature of the growth mixture so that nanostructures (114) are formed on the seed layer via chemical reaction in presence of the growth agent.

Abstract: The present invention relates to a method for manufacturing a plurality of nanostructures comprising the steps of providing a plurality of protruding base structures (104) arranged on a surface of a first substrate (102), providing a seed layer mixture, comprising a solvent/dispersant and a seed material, in contact with the protruding base structures, providing a second substrate arranged in parallel with the first substrate adjacent to the protruding base structures, thereby enclosing a majority of the seed layer mixture between the first and second substrates, evaporating the solvent, thereby forming a seed layer (110) comprising the seed material on the protruding base structures, removing the second substrate, providing a growth mixture, comprising a growth agent, in contact with the seed layer, and controlling the temperature of the growth mixture so that nanostructures (114) are formed on the seed layer via chemical reaction in presence of the growth agent.

Abstract: A method of manufacturing a liquid crystal display device including a TFT substrate with display and peripheral regions. The display region has pixels each having a pixel electrode and a TFT. A counter substrate opposes the TFT substrate and has a color filter formed at a position corresponding to a position at which the pixel electrode is formed above the TFT substrate. The method includes coating, outside of the display region of the TFT substrate, a second alignment film in the shape of a frame, and coating, in the display region, a first alignment film that dries more slowly than the second alignment film. The first and second alignment films are in contact, and the second alignment film is thicker than the first alignment film.

Abstract: In a liquid crystal display device small in the size and having a narrow frame, an alignment film can be coated by ink jet printing, by coating a rapidly drying peripheral alignment film 109 in the shape of a frame to a TFT substrate 100 having a display region having pixel electrode 107 and a peripheral region thereof by ink jet printing, and then coating a display region alignment film 108 drying slower but excellent in the leveling effect by ink jet printing. While the display region alignment film 108 dries slowly, since the peripheral alignment film 109 formed to the periphery functions as a stopper, the shape of the alignment film can be defined accurately, thereby enabling to prevent lowering of the adhesion of the seal member 20 under the effect of the alignment film. This can be applied also on the side of the counter substrate 200.

Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: The present invention prevents an unrubbed portion caused by asperities formed on a surface of an alignment layer of a TFT substrate or a counter substrate. A TFT substrate is disposed on a rubbing stage and a projecting portion is formed on a surface of the TFT substrate by TFT wiring. The projecting portion on the surface causes an unrubbed portion, that is, a rubbing shadow particularly at the downstream of rubbing. In a rubbing step, two rubbing rollers that rotate in different directions are provided and the TFT substrate is rubbed in contact with the two rubbing rollers that rotate in different directions, which eliminates the influence of the rubbing shadow. Thus light leakage is prevented in black display.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: Electrically insulating layers having increased thermal conductivity, as well as associated devices and methods are disclosed. In one aspect, for example, a printed circuit board is provided including a substrate and an electrically insulating layer coated on at least one surface of the substrate, the electrically insulating layer including a plurality of hBN particles bound in a binder material.

Abstract: In a liquid crystal display device small in the size and having a narrow frame, an alignment film can be coated by ink jet printing, by coating a rapidly drying peripheral alignment film 109 in the shape of a frame to a TFT substrate 100 having a display region having pixel electrode 107 and a peripheral region thereof by ink jet printing, and then coating a display region alignment film 108 drying slower but excellent in the leveling effect by ink jet printing. While the display region alignment film 108 dries slowly, since the peripheral alignment film 109 formed to the periphery functions as a stopper, the shape of the alignment film can be defined accurately, thereby enabling to prevent lowering of the adhesion of the seal member 20 under the effect of the alignment film. This can be applied also on the side of the counter substrate 200.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.