Abstract: The invention relates to a method for storing code symbols and additional control information in a processing means of an encoder of a communication system. In particular, the invention relates to the storing of code symbols together with additional control information in an interleaving memory (IM) of an interleaver. According to the invention, a combining means (COM) combines respective data bits (I, Q) forming a respective code symbol with their associated control bits into a control information/code symbol data word of a predetermined number (K) of bits. A control information/code symbol encoding means (CI/CS-ENC) encodes the control information/code symbol data words into encoded data words of a smaller number of bits. This data word with a smaller number of bits is then stored at a particular memory location in the interleaving memory (IM).

Abstract: The invention relates to a time-alignment apparatus and a time-alignment method of a transmitter (TX) of a telecommunication system TELE. Successive data frames (ch1/0, ch2/0, ch3/0, ch4/0, ch8/0, ch300/0) are written to one or two frame memories (RAM1, RAM2) starting at a respective frame start write address (FRST-ADRchy). A third frame memory (RAM3) having a read state is read out in the column direction such that one data symbol of each storage resource (RES1, RES2 . . . RES300) can be output to a modulator unit (BBTX) of the transmitter (TX). The read/write state (WR/RD) of the three frame memories (RAM1, RAM2, RAM3) is cyclically switched through a first to third alignment mode (M1, M2, M3) such that always a first write state memory (RAM1) and a second write state memory (RAM2) are provided. An interleaving process can be carried out together with the time-offset adjustment if the storage resource is constituted by an interleaving matrix.

Abstract: The invention relates to a time-alignment apparatus and a time-alignment method of a transmitter (TX) of a telecommunication system TELE. Successive data frames (ch1/0, ch2/0, ch3/0, ch4/0, ch8/0, ch300/0) are written to one or two frame memories (RAM 1, RAM2) starting at a respective frame start write address (FRST-ADRchy). A third frame memory (RAM3) having a read state is read out in the column direction such that one data symbol of each storage resource (RES1, RES2 . . . RES300) can be output to a modulator unit (BBTX) of the transmitter (TX). The read-write state (WR/RD) of the three frame memories (RAM1, RAM2, RAM3) is cyclically switched through a first lo third alignment mode (M1, M2, M3) such that always a first write state memory (RAM1) and a second write state memory (RAM2) are provided.

Abstract: The invention relates to a converter (CVT) and a conversion method for converting an input data packet stream (IDPS) of consecutive data packets (DP0,0, DP1,0, DP2,0 . . . DPN−1,0) each data packet including user (US0, US1, US2, . . . USN−1) data in the form of a predetermined number (Nsymbol0; Nsymbol1; NsymbolN−1) of consecutive data symbols (S0,0(0), S0,0(1) . . . S0,0(Nsymbol0−1); S1,0(0), S1,0(1) . . . S0,0(Nsymbol0−1); S2,0(0), S2,0(1) . . . S2,0(Nsymbol2−1); . . . SN−1,0(0), SN−1,0(1) . . . SN−1,0(NsymbolN−1−1)) from a plurality of N user channels (ch-0, . . . ,ch-N−1), each user channel having a predetermined transmission rate TR0, TR1, TR2, . . . ,TRn, . . . TRN−1, being defined as a basic transmission rate TRB or an integer multiple TRn=Kn*TRB thereof, into an output data symbol stream (ODSS) in which a respective number Kn of data symbols (S0,0(0); S1,0(0), S1,0(1), S1,0(2), S1,0(3); S2,0(0); . . .