Abstract: A level shifter device comprises a first stage level shifter configured to transform an input signal to a first output signal having a voltage between at least one of a VPS control voltage and a ground or a VDD supply voltage and a VNS control voltage. The level shifter device comprises a second stage level shifter arranged subsequent to the first stage level shifter and configured to transform the first output signal to a second output signal having a voltage between the ground and the VDD supply voltage.

Abstract: A level shifter device comprises a first stage level shifter configured to transform an input signal to a first output signal having a voltage between at least one of a VPS control voltage and a ground or a VDD supply voltage and a VNS control voltage. The level shifter device comprises a second stage level shifter arranged subsequent to the first stage level shifter and configured to transform the first output signal to a second output signal having a voltage between the ground and the VDD supply voltage.

Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.

Abstract: An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.

Abstract: A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.

Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.

Abstract: The invention creates an electronic circuit arrangement for receiving a received electrical signal (101) with a first receiving device (100), a second receiving device (200) and a comparator unit (301) for comparing a second signal difference (207), output by the second receiving device (200), with a target value signal (303) and for outputting a control signal (305) in dependence on the comparison, wherein the control signal (305) controls both the first receiving device (100) and the second receiving device (200) into a respective operating point in such a manner that the amplified second signal difference (207) is held at a level of the target value signal (303) and a first signal difference (107) output from the first receiving device (100) supplies with high accuracy a measure of the received signal (101) with respect to a predetermined reference signal (103).

Abstract: An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.

Abstract: A method of electrostatic discharge (ESD) protection of an electronic circuit includes coupling a first circuit point of the electronic circuit to a first capacitance, coupling a second circuit point of the electronic circuit to a second capacitance, and substantially diverting an ESD voltage pulse occurring at the first circuit point via the second circuit point with the second capacitance.

Abstract: A semiconductor memory device comprises a temperature dependent voltage source for outputting a voltage at its output in dependence on a temperature measured in the semiconductor memory device. At least one memory cell is provided with at least one first transistor. The first transistor includes a first transistor body, which is connected to the output of said temperature dependent voltage source.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: A voltage generator for producing an internal supply voltage has a standby voltage generator and a voltage generator for normal operation that are controlled in common by a reference voltage. In addition, a comparator stage is provided whose switching threshold is set lower than the reference voltage by using a voltage divider that is connected to the reference voltage. The additional comparator stage thus activates the voltage generator for normal operation when the internally produced voltage falls below its switching threshold so that the internal supply voltage is stabilized.

Abstract: A voltage generator for producing an internal supply voltage has a standby voltage generator and a voltage generator for normal operation that are controlled in common by a reference voltage. In addition, a comparator stage is provided whose switching threshold is set lower than the reference voltage by using a voltage divider that is connected to the reference voltage. The additional comparator stage thus activates the voltage generator for normal operation when the internally produced voltage falls below its switching threshold so that the internal supply voltage is stabilized.

Abstract: An integrated circuit has a first voltage generator, which is connected via a first switching element to a contact-making point for external contact making with the circuit. In addition, it has a first digital control device, via which the contact-making point is connected to a control input of the first switching element. In this case, the first control device switches the first switching element on or turns the latter off by a first digital control signal, the level of which is dependent on the potential of the contact-making point. Furthermore, the contact-making point is connected to the input of a second digital control device, which supplies a digital operating mode signal at its output, the level of which operating mode signal is dependent on the potential of the contact-making point.

Abstract: An integrated circuit includes a voltage regulator for generating an internal supply voltage. The voltage regulator has one input for applying an actual value and one input for applying a reference voltage as a desired value. The actual value is generated through the use of a first voltage divider from the internal supply voltage. A sensitivity of the voltage regulator is dependent on a resistance of at least one resistor element of the first voltage divider. A second voltage divider, which is connected parallel to the first voltage divider, has the same voltage divider ratio as the first voltage divider and is activatable and deactivatable by at least one switch element.

Abstract: A circuit configuration for reducing disturbances due to a switching of an output driver. The output driver has a plurality of output driver stages and a delay element. The delay element increases the signal delay of the switch-on or switch-off signals for the output driver stages with an increasing supply voltage.