Abstract: Apparatuses, systems, and methods for a memory refresh watchdog circuit. A memory may include a temperature sensor which sets a value of a refresh multiplier in a mode register. The memory includes a refresh watchdog circuit which determines an expected rate of refresh commands based on a current value of the refresh multiplier. The refresh watchdog circuit measures a rate at which refresh commands are received from a memory controller and compares the measured rate to the expected rate. For example, the refresh watchdog circuit may set a threshold based on the value of the refresh multiplier. The refresh watchdog circuit may change a count value each time a refresh command is received and compare the count value to the threshold. If the count value is less than the threshold, then the refresh watchdog circuit may determine that not enough refresh commands have been received.

Abstract: Memory devices might include a controller for access of an array of memory cells and a differential storage device comprising a pair of gate-connected non-volatile memory cells, wherein the controller is configured to cause the memory device to obtain information indicative of a data value stored in a particular memory cell of the array of memory cells, program additional data to the particular memory cell, determine if a power loss to the memory device is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory device is indicated, selectively program one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.

Abstract: Memory devices might include a controller for access of an array of memory cells and a differential storage device comprising a pair of gate-connected non-volatile memory cells, wherein the controller is configured to cause the memory device to obtain information indicative of a data value stored in a particular memory cell of the array of memory cells, program additional data to the particular memory cell, determine if a power loss to the memory device is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory device is indicated, selectively program one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.

Abstract: Methods of operating memory might include storing information indicative of a data value of a digit of data stored in a particular memory cell of the memory prior to programming a subsequent digit of data to the particular memory cell, programming the subsequent digit of data to the particular memory cell, monitoring a voltage level of a supply voltage to the memory while programming the subsequent digit of data, and, if the voltage level of the supply voltage falls below a threshold while programming the subsequent digit of data and the information indicative of the data value of the digit of data has a particular logic level, causing a change in threshold voltage of one memory cell of a pair of gate-connected non-volatile memory cells, and inhibiting the other memory cell of the pair of gate-connected non-volatile memory cells from a change in threshold voltage.

Abstract: Methods of operating memory might include storing information indicative of a data value of a digit of data stored in a particular memory cell of the memory prior to programming a subsequent digit of data to the particular memory cell, programming the subsequent digit of data to the particular memory cell, monitoring a voltage level of a supply voltage to the memory while programming the subsequent digit of data, and, if the voltage level of the supply voltage falls below a threshold while programming the subsequent digit of data and the information indicative of the data value of the digit of data has a particular logic level, causing a change in threshold voltage of one memory cell of a pair of gate-connected non-volatile memory cells, and inhibiting the other memory cell of the pair of gate-connected non-volatile memory cells from a change in threshold voltage.

Abstract: Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

Abstract: Apparatus including an array of volatile memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of volatile memory cells and having a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level and a second non-volatile memory cell connected between a second isolation gate and the voltage node, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell. The apparatus further logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell.

Abstract: Apparatus having an array of memory cells and a differential storage array might have a controller configured to program first data to a plurality of memory cells of the array of memory cells corresponding to an address of the array of memory cells, program second data to the plurality of memory cells containing the first data, determine if a power loss to the apparatus is indicated while programming the second data, and, if a power loss is indicated, program a first plurality of differential storage devices of the differential storage array responsive to information indicative of a plurality of digits of the first data, program a second plurality of differential storage devices of the differential storage array responsive to information indicative of a plurality of digits of the address, and program a third differential storage device of the differential storage array to have a particular value.

Abstract: Apparatus having an array of memory cells and a differential storage array might have a controller configured to program first data to a plurality of memory cells of the array of memory cells corresponding to an address of the array of memory cells, program second data to the plurality of memory cells containing the first data, determine if a power loss to the apparatus is indicated while programming the second data, and, if a power loss is indicated, program a first plurality of differential storage devices of the differential storage array responsive to information indicative of a plurality of digits of the first data, program a second plurality of differential storage devices of the differential storage array responsive to information indicative of a plurality of digits of the address, and program a third differential storage device of the differential storage array to have a particular value.

Abstract: Methods of operating memory, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of the memory, programming additional data to the particular memory cell, determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory is indicated, programming a first plurality of differential storage devices responsive to the information indicative of the respective data values stored in the plurality of memory cells, programming a second plurality of differential storage devices responsive to the address, and programming a third differential storage device to have a particular value.

Abstract: Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

Abstract: Apparatus including an array of volatile memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of volatile memory cells and having a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level and a second non-volatile memory cell connected between a second isolation gate and the voltage node, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell. The apparatus further logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell.

Abstract: Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

Abstract: Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of an array of volatile memory cells of the apparatus, determining if a power loss to the apparatus is indicated, and, if a power loss to the apparatus is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells of the apparatus responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

Abstract: Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive information indicative of a data value stored in a particular memory cell of the array of memory cells selected for a programming operation. The differential storage device might include a first non-volatile memory cell connected between a first isolation gate and a voltage node configured to receive a first voltage level, and a second non-volatile memory cell connected between a second isolation gate and the voltage node, and logic responsive to an indication of a loss of power to the apparatus and the information indicative of the data value stored in the particular memory cell to store data to the differential storage device, wherein a gate of the second non-volatile memory cell is connected to a gate of the first non-volatile memory cell.

Abstract: Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of an array of volatile memory cells of the apparatus, determining if a power loss to the apparatus is indicated, and, if a power loss to the apparatus is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells of the apparatus responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

Abstract: Methods of operating memory, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of the memory, programming additional data to the particular memory cell, determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

Abstract: A circuit arrangement which, in accordance with its mode of control, operates either as input circuit or as output circuit and includes a series connection with an inverter stage, a filter stage, a cross-current avoiding stage, a switching-on voltage reducing stage, a switch stage, an output driver stage, and a Miller feedback stage, which are configured in the mode of operation as an output circuit, and parallel thereto a Schmitt trigger and an analog switch that can become effective in the mode of operation as input circuit.

Abstract: For an analysis of an electrical behaviour of a specific cell of a monolithically integrated circuit, a simulation model is used which is composed of a fine model part of the cell of interest and a coarse model part of the remainder of the integrated circuit.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.