Patents by Inventor Rainer Cholewa

Rainer Cholewa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8381596
    Abstract: Pressure sensors having a topside boss and a cavity formed using deep reactive-ion etching (DRIE) or plasma etching. Since the boss is formed on the topside, the boss is aligned to other features on the topside of the pressure sensor, such as a Wheatstone bridge or other circuit elements. Also, since the boss is formed as part of the diaphragm, the boss has a reduced mass and is less susceptible to the effects of gravity and acceleration. These pressure sensors may also have a cavity formed using a DRIE or plasma etch. Use of these etches result in a cavity having edges that are substantially orthogonal to the diaphragm, such that pressure sensor die area is reduced. The use of these etches also permits the use of p-doped wafers, which are compatible with conventional CMOS technologies.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 26, 2013
    Assignee: Silicon Microstructures, Inc.
    Inventors: Holger Doering, Rainer Cholewa
  • Publication number: 20110146411
    Abstract: Pressure sensors having a topside boss and a cavity formed using deep reactive-ion etching (DRIE) or plasma etching. Since the boss is formed on the topside, the boss is aligned to other features on the topside of the pressure sensor, such as a Wheatstone bridge or other circuit elements. Also, since the boss is formed as part of the diaphragm, the boss has a reduced mass and is less susceptible to the effects of gravity and acceleration. These pressure sensors may also have a cavity formed using a DRIE or plasma etch. Use of these etches result in a cavity having edges that are substantially orthogonal to the diaphragm, such that pressure sensor die area is reduced. The use of these etches also permits the use of p-doped wafers, which are compatible with conventional CMOS technologies.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: Silicon Microstructures, Inc.
    Inventors: Holger Doering, Rainer Cholewa