Abstract: A method and a device for data processing in an optical communication network are provided, wherein in an energy saving mode of a polarization multiplexing system data signals are transmitted or received via one polarization plane; and wherein components of the transmitter or receiver of the other polarization plane are at least partially operated in a reduced power mode. Furthermore, a communication system is suggested comprising said device.

Abstract: A method and a device for data processing in an optical communication network are provided, wherein in an energy saving mode of a polarization multiplexing system data signals are transmitted or received via one polarization plane; and wherein components of the transmitter or receiver of the other polarization plane are at least partially operated in a reduced power mode. Furthermore, a communication system is suggested comprising said device.

Abstract: A floating point unit of an in-order-processor having a register array for storing a plurality of operands, a pipeline for executing floating point instructions with a plurality of stages, each stage having a stage register, data input registers (1A, 1B, 1C) for keeping operands to be processed. The data input registers form the first stage register of the pipeline. An input port loads operands from outside said floating point unit into one of said data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port, and the output of which is provided to the data input registers (1A, 1B, 1C), such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers (1A, 1B, 1C) from a respective bypass-register without a delay caused by additional pipeline stages to be propagated through.

Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a `0` is fast. Reading a `1` is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current.

Abstract: For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.

Abstract: A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder, an AND gate connected to a clock signal, the AND gate enabling a write port coupled to the latch of a memory cell. In the second stage, a read path is set up comprising a read address decoder selecting a read port, through which data is read from the cell latch to a data out buffer. To minimize the write-thru access time, the synchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses.

Abstract: An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which can be directly controlled with TTL levels without a level converter consisting of bipolar transistors being inserted. For that purpose, the input electrode of the bootstrap capacitor of the dynamically operating charge-up circuit is connected to the output of an inverter following the input circuit. Furthermore a discharge branch is provided for the node of the dynamically operating charge-up circuit. With its other end, together with the gate of the charge-up field effect transistor of the dynamic charge-up circuit, the discharge branch is connected to the output of another inverter following the first one.

Abstract: This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

Abstract: A field effect transistor driver circuit responsive to a single input pusle generates a highly loadable output clock pulse with short rise and fall times, the rising edge being shifted relative to said input pulse by a controllable delay time but the trailing edge remaining practically undelayed. This advantageous pulse form is achieved through an improved controlling of a bootstrap output stage. Two preceding stages, i.e., a transmission gate and a delay stage supply two out-of-phase control pulses with high amplitudes and steep edges. Of essential importance is the novel delay stage which is designed as push-pull stage with a load FET and a driver FET. The gate of the load FET is controlled by the output pulse of the bootstrap stage 2 fed back via a third FET and by a capacitively coupled-in input pulse at the drain, whereas the gate of driver FET is controlled from the bootstrapped output of the transmission gate. The connecting point of load and driver FET represents the output of the delay stage.

Abstract: To the known sense latch already existing in a bit line pair in an FET memory, and to the two bit switches in each bit line another latch is arranged in series which furthermore is coupled to the common data input and output via a write driver on the one side and a read driver on the other. Both latches are of an identical structure and controlled by the same pulses in the read as well as in the write phase. The data path via the write driver and the read driver up to, or from, the additional latch is respectively designed as unidirectional double rail line, and selectively connectable via the bit switches with the bidirectional double rail line to the respective bit line pair.

Abstract: Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.