Abstract: A digital signal constituted by a stream of bits is so encoded that its running digital sum (RDS) is confined to a range defined by predetermined lower and upper permissible limits, i.e., absent transmission error. Instead of using a forwards-backwards digital counter to monitor the RDS, with its associated expense and relatively high power consumption when high transmission rates are involved, use is made of an analog integrator which integrates the digital signal to be monitored and generates an analog RDS signal. A digit-error signal is generated when the analog RDS signal attempts to exceed a predetermined analog value corresponding to the upper permissible limit of the RDS or to fall below a predetermined analog value corresponding to the lower permissible limit of the RDS.