Patents by Inventor Rainer Dudek

Rainer Dudek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package with interlocked connection
    Patent number: 10090216
    Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall, Michael Goroll, Rainer Dudek
  • Semiconductor Package With Interlocked Connection
    Publication number: 20170170082
    Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 15, 2017
    Inventors: Georg Meyer-Berg, Reinhard Pufall, Michael Goroll, Rainer Dudek
  • Semiconductor module with interlocked connection
    Patent number: 9627305
    Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall, Michael Goroll, Rainer Dudek
  • SEMICONDUCTOR MODULE WITH INTERLOCKED CONNECTION
    Publication number: 20150014845
    Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Georg Meyer-Berg, Reinhard Pufall, Michael Goroll, Rainer Dudek