Abstract: A method is provided in which intermediate sized structures can be filled without forming voids during the fill process. The methods involve use of a sequence of CVD/PVD/CVD/PVD steps. The methods are especially effective for filling “intermediate” size features in damascene and dual damascene structures.

Abstract: A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Abstract: A process of forming a wiring in a semiconductor interlayer dielectric, include simultaneously patterning a via and a slotted line in the interlayer diectric, simultaneously etching the via and the slotted line, and simultaneously filling the via and the slotted line with a metal.

Abstract: A method for forming self-aligned features for semiconductor devices includes the steps of providing a first layer including a reflective material on a surface of the first layer, a second layer formed on the first layer, and a resist layer formed on the second layer, providing radiation through the resist layer and the second layer wherein the radiation is reflected from the reflective material back to the resist layer thereby increasing irradiation of the resist layer over the reflective material and developing the resist layer. A semiconductor device in accordance with the invention includes a first layer with reflective structures therein. A second layer is formed on the first layer, and a patterned resist layer is formed on the second layer.

Abstract: A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Abstract: A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.