Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

Abstract: The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the CMP process, high erosion rates for iridium and a high selectivity relative to silicon oxide are achieved upon employment of a polishing fluid that contains 1 through 6% by weight abrasive particles, 2 through 20% by weight of at least one oxidation agent selected from the group comprising Ce(IV) salts, salts of chloric acid, salts of peroxodisulfuric acid, hydrogen peroxide and salts of hydrogen peroxide, and 74 through 97% by weight water. This enables the structuring of iridium layers with the assistance of an oxide mask and a CMP process.

Abstract: The integrated circuit has a test circuit, which is connected to an input terminal of the integrated circuit via a line connection. An isolating device is provided between an input terminal of the test circuit in order to completely isolate the line connection between the test circuit and the input terminal after the test circuit has performed a test procedure.

Abstract: It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the spine center. An encoder is additionally provided, which is connected to the n inputs on an input side and to one end of the interconnects on an output side and which is likewise disposed on one side of the spine center. In this case, a number n of the inputs is greater than a number of the interconnects. A decoder, which is connected to the other end of the interconnects on the input side and to n outputs on the output side, is disposed on the other side of the spine center.

Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.

Abstract: The invention relates to a method for producing at least one capacitor structure, comprising the following steps: providing a substrate, producing a first electrode on said substrate, producing a mask, whereby the first electrode is disposed in an opening of said mask, and applying at least one dielectric layer and at least one conductive layer for a second eletrode. The surface of the part of the conductive layer that is applied in the opening of the mask is substantially disposed below the surface of the mask. The conductive layer and the dielectric layer are structured by polishing so that a capacitor structure is produced.

Abstract: The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

Abstract: The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the CMP process, high erosion rates for iridium and a high selectivity relative to silicon oxide are achieved upon employment of a polishing fluid that contains 1 through 6% by weight abrasive particles, 2 through 20% by weight of at least one oxidation agent selected from the group comprising Ce(IV) salts, salts of chloric acid, salts of peroxodisulfuric acid and hydrogen peroxide as well as the salts thereof, and 97 through 74% by weight water. This enables the structuring of iridium layers with the assistance of an oxide mask and a CMP process.

Abstract: The integrated circuit has a test circuit, which is connected to an input terminal of the integrated circuit via a line connection. An isolating device is provided between an input terminal of the test circuit in order to completely isolate the line connection between the test circuit and the input terminal after the test circuit has performed a test procedure.

Abstract: It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the spine center. An encoder is additionally provided, which is connected to the n inputs on an input side and to one end of the interconnects on an output side and which is likewise disposed on one side of the spine center. In this case, a number n of the inputs is greater than a number of the interconnects. A decoder, which is connected to the other end of the interconnects on the input side and to n outputs on the output side, is disposed on the other side of the spine center.

Abstract: A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.

Abstract: An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.

Abstract: A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

Abstract: A method for optically measuring layer thickness in accordance with the present invention includes the steps of providing a first metal layer on a semiconductor device structure, providing a second metal layer on the first metal layer, forming a dielectric layer over the second metal layer and directing light onto the structure such that light reflected from a surface of the dielectric layer and a surface of the second metal layer create an interference pattern from which the dielectric layer thickness is measured. A system for optically measuring layer thickness includes a semiconductor device to be measured. The semiconductor device includes a first metal layer, a second metal layer disposed on the first metal layer, the second metal layer having an arcuate shaped top surface and a dielectric layer disposed on the second metal layer.

Abstract: An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).

Abstract: Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.