Patents by Inventor Rainer Giedigkeit

Rainer Giedigkeit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8791509
    Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Patrick Press, Rainer Giedigkeit, Jan Hoentschel
  • Patent number: 8673668
    Abstract: When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr, Rainer Giedigkeit
  • Patent number: 8501545
    Abstract: In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 6, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Grillberger, Matthias Lehr, Rainer Giedigkeit
  • Publication number: 20130049124
    Abstract: An MOSFET device having a Silicide layer of uniform thickness and which is substantially free of “Spotty” NiSi-type holes, and methods for its fabrication, are provided. One such method involves simultaneously depositing a metal layer (e.g. Ni) over the active and open areas of a semiconductor substrate. The depth to which some or all of the metal is transferred into the substrate is determined by thermal budget. A rapid thermal annealing process is employed to produce a NiSi layer of a uniform thickness in both the active and open areas. Upon achieving a NiSi layer of a desired thickness, the excess metal is removed from the substrate surface.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Clemens Fitz, Stephan Waidmann, Stefan Flachowsky, Peter Baars, Rainer Giedigkeit
  • Patent number: 8338654
    Abstract: Selective hydrogenation of unsaturated hydrocarbon compounds, e.g. of acetylene to ethylene, uses a hydrogenation catalyst comprising an ordered intermetallic compound. The ordered intermetallic compound comprises at least one metal of type A capable of activating hydrogen, and at least one metal of type B not capable of activating hydrogen. The structure of the ordered intermetallic compound is such that the type A metal is mainly surrounded by atoms of the type B metal.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: December 25, 2012
    Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften E.V.
    Inventors: Rainer Giedigkeit, Marc Armbruester, Kirill Kovnir, Juri Grin, Robert Schloegl, Juergen Osswald, Thorsten Kessler, Rolf E. Jentoft
  • Publication number: 20120001174
    Abstract: When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.
    Type: Application
    Filed: December 10, 2010
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Maciej Wiatr, Rainer Giedigkeit
  • Publication number: 20110266638
    Abstract: A metal silicide in sophisticated semiconductor devices may be provided in a late manufacturing stage on the basis of contact openings, wherein the deposition of the contact material, such as tungsten, may be efficiently combined with the silicidation process. In this case, the thermally activated deposition process may initiate the formation of a metal silicide in highly doped semiconductor regions.
    Type: Application
    Filed: December 9, 2010
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai Frohberg, Rainer Giedigkeit, Robert Binder, Stephan Waidmann
  • Publication number: 20110244632
    Abstract: In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.
    Type: Application
    Filed: December 8, 2010
    Publication date: October 6, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Michael Grillberger, Matthias Lehr, Rainer Giedigkeit
  • Publication number: 20100133614
    Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.
    Type: Application
    Filed: November 17, 2009
    Publication date: June 3, 2010
    Inventors: Sven Beyer, Patrick Press, Rainer Giedigkeit, Jan Hoentschel
  • Publication number: 20090221861
    Abstract: The present invention relates to a process for the hydrogenation, in particular the selective hydrogenation of unsaturated hydrocarbon compounds using a hydrogenation catalyst comprising an ordered intermetallic compound. The ordered intermetallic compound comprises at least one metal of type A capable of activating hydrogen, and at least one metal of type B not capable of activating hydrogen, and the structure of the ordered intermetallic compound is such that at least one king of type A metals is mainly surrounded by atoms of the metal of type B. According to another aspect, the present invention is concerned with a catalyst comprising a support and the above ordered intermetallic compound supported on the support. According to still another aspect, the invention pertains to the use of a binary Pd—Ga ordered intermetallic compound as a catalyst. The hydrogenation process and catalysts of the present invention achieve a selectivity to the target compounds, e.g.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 3, 2009
    Applicant: Max-Planck-Gesellschaft zur Foerderung Der Wissenschaften E.V.
    Inventors: Rainer Giedigkeit, Marc Armbruester, Kirill Kovnir, Juri Grin, Robert Schloegl, Juergen Osswald, Thorsten Ressler, Rolf E. Jentoft