Patents by Inventor Rainer Höhler
Rainer Höhler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11256426Abstract: In an example embodiment, a device comprises a non-volatile memory and wear leveling control circuitry. The non-volatile memory comprises logical memory sectors mapped to physical memory sectors, and a supervisory memory sector configured to store a mapping of the logical memory sectors to memory partitions with user-defined boundaries. The wear leveling control circuitry is configured to: receive and store, in the mapping, wear leveling parameters based on user input, where each memory partition is associated with a wear leveling parameter indicating whether that memory partition is excluded from wear leveling; and determine and apply, to the non-volatile memory, wear leveling characteristics based on the wear leveling parameters, where the wear leveling characteristics identify an amount of wear leveling allowed for each of the memory partitions.Type: GrantFiled: October 16, 2019Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventors: Mark Alan McClain, Willy Obereiner, Rainer Hoehler
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Publication number: 20200192583Abstract: In an example embodiment, a device comprises a non-volatile memory and wear leveling control circuitry. The non-volatile memory comprises logical memory sectors mapped to physical memory sectors, and a supervisory memory sector configured to store a mapping of the logical memory sectors to memory partitions with user-defined boundaries. The wear leveling control circuitry is configured to: receive and store, in the mapping, wear leveling parameters based on user input, where each memory partition is associated with a wear leveling parameter indicating whether that memory partition is excluded from wear leveling; and determine and apply, to the non-volatile memory, wear leveling characteristics based on the wear leveling parameters, where the wear leveling characteristics identify an amount of wear leveling allowed for each of the memory partitions.Type: ApplicationFiled: October 16, 2019Publication date: June 18, 2020Applicant: Cypress Semiconductor CorporationInventors: Mark Alan McClain, Willy Obereiner, Rainer Hoehler
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Patent number: 10489064Abstract: Disclosed herein are systems, methods, and devices for user configurable wear leveling of non-volatile memory devices. Devices include a non-volatile memory including a plurality of physical memory portions, where each of the plurality of physical memory portions is configured to be mapped to a logical memory portion of a plurality of logical memory portions. Devices may also include wear leveling control circuitry configured to receive a plurality of wear leveling parameters, and further configured to determine a plurality of wear leveling characteristics based on the plurality of wear leveling parameters received, where the plurality of wear leveling characteristics identify an amount of wear leveling allowed for each of the plurality of logical memory portions.Type: GrantFiled: December 22, 2016Date of Patent: November 26, 2019Assignee: Cypress Semiconductor CorporationInventors: Mark Alan McClain, Willy Obereiner, Rainer Hoehler
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Publication number: 20180095678Abstract: Disclosed herein are systems, methods, and devices for user configurable wear leveling of non-volatile memory devices. Devices include a non-volatile memory including a plurality of physical memory portions, where each of the plurality of physical memory portions is configured to be mapped to a logical memory portion of a plurality of logical memory portions. Devices may also include wear leveling control circuitry configured to receive a plurality of wear leveling parameters, and further configured to determine a plurality of wear leveling characteristics based on the plurality of wear leveling parameters received, where the plurality of wear leveling characteristics identify an amount of wear leveling allowed for each of the plurality of logical memory portions.Type: ApplicationFiled: December 22, 2016Publication date: April 5, 2018Inventors: Mark Alan McClain, Willy Obereiner, Rainer Hoehler
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Patent number: 7193919Abstract: A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command signals received by a memory device and refreshing the several memory banks based on the monitored command signals so as to avoid unnecessary power consumption for refreshing particular ones of the several memory banks with irrelevant contents.Type: GrantFiled: October 12, 2005Date of Patent: March 20, 2007Assignee: Infineon Technologies AGInventor: Rainer Hoehler
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Publication number: 20060087902Abstract: A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command signals received by a memory device and refreshing the several memory banks based on the monitored command signals so as to avoid unnecessary power consumption for refreshing particular ones of the several memory banks with irrelevant contents.Type: ApplicationFiled: October 12, 2005Publication date: April 27, 2006Inventor: Rainer Hoehler
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Patent number: 7024570Abstract: A random access memory with a low power mode indicator. The random access memory includes a state machine for generating a power mode output signal. A power mode pin control circuit is connected to the state machine for receiving the power mode output signal. A power mode pin is connected to the power mode pin control circuit for providing an output indicative of the power mode output signal received from the state machine.Type: GrantFiled: October 18, 2002Date of Patent: April 4, 2006Assignee: Infineon Technologies North America Corp.Inventor: Rainer Hoehler
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Patent number: 6956782Abstract: A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command signals received by a memory device and refreshing the several memory banks based on the monitored command signals so as to avoid unnecessary power consumption for refreshing particular ones of the several memory banks with irrelevant contents.Type: GrantFiled: September 30, 2003Date of Patent: October 18, 2005Assignee: Infineon Technologies AGInventor: Rainer Hoehler
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Publication number: 20050078538Abstract: A method of refreshing memory banks of a memory device that receives command signals from a memory controller. The method including monitoring command signals received by the memory device and refreshing several memory banks of the memory device based on the monitored command signals so as to avoid unnecessary power consumption for refreshing the several memory banks.Type: ApplicationFiled: September 30, 2003Publication date: April 14, 2005Inventor: Rainer Hoehler
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Publication number: 20050068826Abstract: A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command signals received by a memory device and refreshing the several memory banks based on the monitored command signals so as to avoid unnecessary power consumption for refreshing particular ones of the several memory banks with irrelevant contents.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventor: Rainer Hoehler
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Patent number: 6779124Abstract: The circuit has a clock input for supplying a first clock signal and a clock generator for generating a second clock signal, said clock generator being phase-locked with respect to the first clock signal. The clock output of the clock generator is connected to a control input of a data transmission unit used for outputting data from the circuit and/or for reading into the circuit essentially in synchronism with the first clock signal. The clock generator has at least two control loops connected in succession which are used for controlling the phase angle of the second clock signal, the first control loop being used to generate from the first clock signal at least two intermediate clock signals, each of which has a particular phase angle with respect to the first clock signal, and the second control loop being used to generate the second clock signal from the intermediate clock signals.Type: GrantFiled: March 19, 2001Date of Patent: August 17, 2004Assignee: Siemens AktiengesellschaftInventors: Rainer Höhler, Gunnar Krause
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Publication number: 20040078611Abstract: A random access memory with a low power mode indicator. The random access memory includes a state machine for generating a power mode output signal. A power mode pin control circuit is connected to the state machine for receiving the power mode output signal. A power mode pin is connected to the power mode pin control circuit for providing an output indicative of the power mode output signal received from the state machine.Type: ApplicationFiled: October 18, 2002Publication date: April 22, 2004Inventor: Rainer Hoehler
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Publication number: 20040059954Abstract: A low power mode system and method for a random access memory. A timer is provided for tracking a time period that has elapsed since a last memory access command was received by the random access memory. A comparator is connected to the timer for comparing said time period that has elapsed since a last memory access command was received by the random access memory with a predetermined threshold value. A state machine is connected to the comparator for placing said random access memory in a lower power mode when the time period exceeds the predetermined threshold value.Type: ApplicationFiled: September 20, 2002Publication date: March 25, 2004Inventor: Rainer Hoehler
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Patent number: 6667919Abstract: A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer circuit for supplying a first voltage level to one of at least one true bitline or at least one complement bitline during a test mode; an equalizing line for coupling a plurality of equalizer circuits along a wordline; and a comparator for comparing a second voltage on the equalizing line during the test mode to a reference voltage, wherein if the second voltage is less than the reference voltage, the wordline is defective.Type: GrantFiled: September 26, 2002Date of Patent: December 23, 2003Assignee: Infineon Technologies, AGInventors: David Suitwai Ma, Paul Edward Brucke, Rainer Hoehler
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Patent number: 6639958Abstract: The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for rapidly adjusting the DLL circuit is converted into a delayed control signal, which is kept constant with the rising edge of a counter clock signal. This prevents instabilities of the counter value from occurring.Type: GrantFiled: March 13, 2000Date of Patent: October 28, 2003Assignee: Infineon Technologies AGInventors: Rainer Höhler, Mathias Von Borcke