Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry connected between a high voltage source and a low voltage source. The core circuitry may include multiple transistors including a first transistor of a first polarity type and a second transistor of a second polarity type that is different than the first polarity type. The integrated circuit may include voltage regulation circuitry connected between an external positive voltage source and ground. The voltage regulation circuitry may operate to provide the low voltage source to the core circuitry. The low voltage source may be equal to or higher than ground. The voltage regulation circuitry may further operate to body bias the multiple transistors with a single voltage that is applied to a body terminal of the first transistor and the second transistor.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry connected between a high voltage source and a low voltage source. The core circuitry may include multiple transistors including a first transistor of a first polarity type and a second transistor of a second polarity type that is different than the first polarity type. The integrated circuit may include voltage regulation circuitry connected between an external positive voltage source and ground. The voltage regulation circuitry may operate to provide the low voltage source to the core circuitry. The low voltage source may be equal to or higher than ground. The voltage regulation circuitry may further operate to body bias the multiple transistors with a single voltage that is applied to a body terminal of the first transistor and the second transistor.

Abstract: Methods and devices are described, including a near-field communications (NFC) or radio frequency identification (RFID) device comprising an NFC or RFID circuit, an antenna having at least a first terminal, a first rectifier connected to the first terminal of the antenna, a switch between the first rectifier and the NFC or RFID circuit, a voltage detector for detecting a voltage in the device caused by a signal received at the antenna, and a control module for controlling the switch, wherein when the voltage exceeds a threshold magnitude, the control module controls the switch to be in an open state and, after a predetermined time period, determines whether the voltage still exceeds the threshold magnitude and, if the voltage still exceeds the predetermined magnitude, controls the switch to be in the open state.

Abstract: A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.

Abstract: A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.

Abstract: Methods of fabricating ultra-low power transistors are described using advanced technology nodes (e.g. 40 nm or less). In an embodiment, by optimizing a MOSFET to a different point, i.e. for low junction off (or leakage) current rather than speed/on current, a MOSFET can be produced which still meets the HCl reliability specification but has significantly reduced power consumption when off, e.g. half to one third of the standard off current. At this new optimisation point, the LDD dose is reduced to a level (e.g. 10-20% of the standard LDD dose) such that if it is reduced further, the device will no longer pass the HCl reliability specification. This is in contrast to standard MOSFETs which are optimized for speed/on current and have an LDD dose which, if increased further, would cause the device to no longer pass the HCl reliability specification.

Abstract: A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.

Abstract: Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.

Abstract: Methods and devices are described, including a near-field communications (NFC) or radio frequency identification (RFID) device comprising an NFC or RFID circuit, an antenna having at least a first terminal, a first rectifier connected to the first terminal of the antenna, a switch between the first rectifier and the NFC or RFID circuit, a voltage detector for detecting a voltage in the device caused by a signal received at the antenna, and a control module for controlling the switch, wherein when the voltage exceeds a threshold magnitude, the control module controls the switch to be in an open state and, after a predetermined time period, determines whether the voltage still exceeds the threshold magnitude and, if the voltage still exceeds the predetermined magnitude, controls the switch to be in the open state.

Abstract: There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with conventional receivers lowers power consumption. Quality metrics in receiving the data (e.g. packet error rate, etc) are not adversely affected by setting a programmable phase shift in the sampling frequency. The programmable shift can be selected through a calibration process using a known sequence of symbols, such as the short training field in 802.11 standards.

Abstract: An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track.

Abstract: A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line, in an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.