Patents by Inventor Rainer Holmer

Rainer Holmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8173534
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 8, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Publication number: 20110147471
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Patent number: 7911036
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: March 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Patent number: 7660175
    Abstract: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 9, 2010
    Assignee: Infineon Technologies AG
    Inventors: Dieter Kohlert, Erhard Sixt, Rainer Holmer, Georg Seidemann, Berthold Schuderer, Gunther Mackh, Sabine Penka, Grit Schwalbe-Dietrich, Bernhard Duschinger, Josef Hermann
  • Publication number: 20090219773
    Abstract: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Dieter Kohlert, Erhard Sixt, Rainer Holmer, Georg Seidemann, Berthold Schuderer, Gunther Mackh, Sabine Penka, Grit Schwalbe-Dietrich, Bernhard Duschinger, Josef Hermann
  • Publication number: 20070178612
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Application
    Filed: January 11, 2007
    Publication date: August 2, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stephan Bradl, Rainer Holmer