Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Generating a description of compiler code selector rules from an architecture description. A method comprises accessing a target architecture model written in an architecture description language (ADL) and extracting semantic information therefrom to generate a plurality of semantic statements. Rules that map from source code operations to semantic patterns are accessed. The semantic statements are searched for matches for the semantic patterns to generate mappings that serve as a description of compiler code selector rules.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: A method of automatically extracting information from an architecture description. A memory resident directed acyclic graph data structure comprising nodes representing instructions and edges whose weights represent dependencies between pairs of instructions is constructed. A list of ready nodes are maintained in the directed acyclic graph. A list of nodes not scheduled is maintained. And, it is determined whether the next instruction to be scheduled is to be taken from the list of ready nodes or from the list of nodes not yet scheduled.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: Generating a simulator from an architecture description. A target architecture model described in an architecture description language (ADL) is accessed. The model comprises a semantic representation of an instruction set for the target architecture. The semantic representation is translated to a behavioral representation. The simulator is automatically generated from the behavioral representation. A compiler may also be generated from the semantic representation.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.