Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: A communication system includes a data exchange interface which is coupled via an internal bus to a microprocessor and a DMA unit. For controlling the data exchange, the interface transmits control signals either to a microprocessor or a DMA unit. The control signals are acknowledged each time. For realizing an efficient data exchange via the interface, the interface is an I.sup.2 C bus interface with minimum load of the microprocessor, and transmits a first group of control signals by a first control line to the DMA unit and a second group of control signals by a second control line to the microprocessor. By respective settings of the interface, a selectable part of the control circuitry may be transferred from the microprocessor to the DMA unit. The total number and type of control signals (interrupts) which correspond each to a specific mode of the interface may be retained.