Abstract: According to various embodiments, a data processing device is described, comprising a data processing circuit, a memory, configured to store data in form of multiple pages, each page comprising a plurality of data words, a memory controller and a memory interface circuit, configured to store, for each page, user data in multiple data words of the page and error checking code bits for the multiple data words in one or more additional data words of the page, wherein, for at least some of the multiple additional data words, the error checking code bits are included in the same additional data word.

Abstract: An apparatus for driving a motor comprising a first plurality of neurons of neural network circuitry, motor circuitry, and a second plurality of neurons of the neural network circuitry. The first plurality of neurons is configured to generate a first cycle value based on a target speed. The motor circuitry is configured to control, based on the first cycle value, a set of switching elements to drive the motor. The second plurality of neurons is configured to train the second plurality of neurons to generate, based on a resulting speed value for the motor that occurs when the motor circuitry has controlled the set of switching elements to drive the motor based on the first cycle value, a second cycle value to minimize a difference between the second cycle value and the first cycle value.

Abstract: An apparatus for driving a motor includes a plurality of neurons of neural network circuitry and motor circuitry. The plurality of neurons are configured to generate a cycle value based on a target speed, based on a speed value associated with the motor at a particular time, and based on a current value associated with the motor at the particular time. The plurality of neurons is configured to be trained to generate the cycle value to minimize an error between the cycle value and a training cycle value for each training vector of a plurality of training vectors. The apparatus is configured to have generated the plurality of training vectors. The motor circuitry is configured to control, based on the cycle value, a set of switching elements to drive the motor.

Abstract: An apparatus for driving a motor includes a plurality of neurons of neural network circuitry and motor circuitry. The plurality of neurons are configured to generate a cycle value based on a target speed, based on a speed value associated with the motor at a particular time, and based on a current value associated with the motor at the particular time. The plurality of neurons is configured to be trained to generate the cycle value to minimize an error between the cycle value and a training cycle value for each training vector of a plurality of training vectors. The apparatus is configured to have generated the plurality of training vectors. The motor circuitry is configured to control, based on the cycle value, a set of switching elements to drive the motor.

Abstract: An apparatus for driving a motor comprising a first plurality of neurons of neural network circuitry, motor circuitry, and a second plurality of neurons of the neural network circuitry. The first plurality of neurons is configured to generate a first cycle value based on a target speed. The motor circuitry is configured to control, based on the first cycle value, a set of switching elements to drive the motor. The second plurality of neurons is configured to train the second plurality of neurons to generate, based on a resulting speed value for the motor that occurs when the motor circuitry has controlled the set of switching elements to drive the motor based on the first cycle value, a second cycle value to minimize a difference between the second cycle value and the first cycle value.

Abstract: A memory module includes a first printed circuit board, wherein some of the memory chips in each of first and second ranks of memory chips are assembled on one side of the printed circuit board and others of the first and second ranks are assembled on the other side of the printed circuit board. First and second registers are respectively connected to the first and second address buses for respectively addressing the first and second ranks of memory chips. Since the addresses buses are separate for the two ranks, it is possible to activate only the address bus associated with the particular rank being addressed. In this manner, address activation power is saved by not activating the address bus of the other rank which is not addressed. Due to less power dissipation, it is possible to operate the memory module without a full DIMM heat spreader.