Patents by Inventor Rainer R. Hadwiger

Rainer R. Hadwiger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bus arbitration method employing a table of slots suitably distributed amongst bus masters
    Patent number: 6895459
    Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: May 17, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Rainer R. Hadwiger, Paul D. Krivacek, Jørn Sørensen, Palle Birk
  • Bus architecture and shared bus arbitration method for a communication device
    Patent number: 6738845
    Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: May 18, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Rainer R. Hadwiger, Paul D. Krivacek, Jørn Sørensen, Palle Birk
  • Bus architecture and shared bus arbitration method for a communication processor
    Publication number: 20040049293
    Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 11, 2004
    Applicant: Analog Devices, Inc.
    Inventors: Rainer R. Hadwiger, Paul D. Krivacek, Joern Soerensen, Palle Birk