Abstract: The disclosure provides synthetic (e.g. recombinant) pneumococcal saccharide comprising one or more repeat unit(s) ?4)-?-D-Glcp-(1?3)-[[?-L-Rhap-(1?2)]-[Gro-(2?P?3)]-?-D-Galp-(1?4)]-?-L-Rhap-(1?. Also provided are conjugates comprising a ?4)-?-D-Glcp-(1?3)-[[?-L-Rhap-(1?2)]-[Gro-(2?P?3)]-?-D-Galp-(1?4)]-?-L-Rhap-(1?, immunogenic compositions, vaccines and their use in preventing or treating infection by Streptococcus pneumoniae.

Abstract: The present invention provides a compound of formula (I) or a pharmaceutically acceptable salt thereof, a method for manufacturing the compounds of the invention, and its therapeutic uses. The present invention further provides a combination of pharmacologically active agents and a pharmaceutical composition.

Abstract: A method for manufacturing a compressor impeller or rotor including a hub that carries blades, involving a step of manufacturing a hub which includes all or some of the blades, and a step of additive manufacture by adding localised material using a method such as the LMD process to form or finish each blade.

Abstract: Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.

Abstract: Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.

Abstract: A heat-exchange architecture for exhaust of a turbine engine, including heat-exchange elements partially obstructing a hot exhaust gases stream. In an architecture built into an exhaust line for gas streams of a turbine engine, the turbine engine is a turboshaft engine including a gas generator and a free turbine supplying power to a shaft via a through-shaft and an upstream reduction gear. An annular plate-shaped exchanger is installed in the axisymmetric portion of the ejector. The exchanger includes inlet and outlet channels, connected to the inlet and outlet of a central channel wound into a helix shape or sine curve in the annular plate. The channels are connected at the other ends to mechanical or electromechanical mechanisms for recovering and recycling energy. The energy is recovered via a cold fluid heated in the central channel by transfer of heat from residual gases.

Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e.g., by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies.

Abstract: Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e.g., by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies.

Abstract: A heat-exchange architecture for exhaust of a turbine engine, including heat-exchange elements partially obstructing a hot exhaust gases stream. In an architecture built into an exhaust line for gas streams of a turbine engine, the turbine engine is a turboshaft engine including a gas generator and a free turbine supplying power to a shaft via a through-shaft and an upstream reduction gear. An annular plate-shaped exchanger is installed in the axisymmetric portion of the ejector. The exchanger includes inlet and outlet channels, connected to the inlet and outlet of a central channel wound into a helix shape or sine curve in the annular plate. The channels are connected at the other ends to mechanical or electromechanical mechanisms for recovering and recycling energy. The energy is recovered via a cold fluid heated in the central channel by transfer of heat from residual gases.

Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device.

Abstract: An apparatus, method, and system for electronic device packaging having stacked dice are disclosed herein. A first die has a through silicon via formed therethrough. A second die is landed on the through silicon via of the first die. A mount having a lead is coupled to the through silicon via of the first die.

Abstract: The present invention relates to a novel, reliable, and forgery-proof method for temperature-induced marking of glass and coating compositions for use in this marking and detection methods for checking the performance of the heat treatment in glass.

Abstract: In the case of a system for controlling a motorcycle air bag with respect to the sitting position of a motorcycle occupant, a distance measuring device measures the distance of the motorcycle occupant with respect to the motorcycle, and an adaptation device controls a motorcycle air bag corresponding to this distance.

Abstract: Digital information is processed for transmission in a communication system using a hidden puncturing technique. The digital information is encoded using a channel code having at least one puncturing pattern associated therewith. The puncturing pattern is preferably a rate compatible puncturing pattern. In accordance with the invention, there is no puncturing of the channel code applied at a transmitter side of the system. Instead, the resulting channel coded bits are assigned to different sections of a digital sideband or other portion of a frequency spectrum of the system, based at least in part on the puncturing pattern. The coded channel bits are then transmitted through the system in the assigned sections, and can be decoded at different code rates in a receiver of the system depending on which of the sections are used in the decoding process.

Abstract: A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.

Abstract: A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.

Abstract: A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP also includes a base region of a second conductivity type formed by a graded channel implant and a well region of a second conductivity type, the well region contacting the base region, the buried region and a base contact. Additionally, there are collector contacts and emitter contacts of a first conductivity type. The lightly doped collector region results in a large Early voltage and the base region provides for a high current gain.

Abstract: A vertically diffused FET (10) is fabricated on a semiconductor die (11) that includes an N+ substrate (12) and an N− epitaxial layer (14). The FET (10) has a source region (36) and a channel region (38) near a front surface (15) of the epitaxial layer (14), and a drain region in the substrate (12). A trench (22) extends through the epitaxial layer (14) to the substrate (12). A conductive layer (24) fills the trench (22), thereby forming a conductive plug (25) electrically coupled to the substrate (12). The conductive plug (25) forms a top side drain electrode of the FET (10).