Abstract: An embodiment of the invention provides a memory on a semiconductor device that has a plurality of memory areas where each memory area has a plurality of consecutive bits. Further, the semiconductor device includes a tag memory having a plurality of trace tags, each trace tag including at least one bit. Each memory area of the memory is mapped to a trace tag that indicates whether the respective memory area is selected for tracing or not. Each memory area and the assigned trace tag are read out and address of the memory area is forwarded to a trace module when an assigned trace tag indicates that the memory area is selected for tracing. When the assigned trace tag indicates that the memory area is not selected for tracing, data and address is discarded.

Abstract: An embodiment of the invention provides a memory on a semiconductor device that has a plurality of memory areas where each memory area has a plurality of consecutive bits. Further, the semiconductor device includes a tag memory having a plurality of trace tags, each trace tag including at least one bit. Each memory area of the memory is mapped to a trace tag that indicates whether the respective memory area is selected for tracing or not. Each memory area and the assigned trace tag are read out and address of the memory area is forwarded to a trace module when an assigned trace tag indicates that the memory area is selected for tracing. When the assigned trace tag indicates that the memory area is not selected for tracing, data and address is discarded.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met, and recovering in a recovering step back from any of the nx escalation levels to a previous level or mode, if a de-escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: A switch state detector for use in a system wherein a plurality of n switches (S1, . . . , Sn) produces on a single line (22) a number of discrete voltage levels each representative of one particular state of open and closed switches. The switch state detector comprises a plurality of reference voltage sources each of which corresponds to one of the discrete voltage levels and a set of comparators (C1, . . . , Cm-1) each having a first input connected to the single line (22) and a second input connected to one of the reference voltage sources. The switch state detector further comprises a decoder (24) with inputs receiving the outputs from the comparators (C1, . . . , Cm-1) and with outputs (28) providing a digital representation of the particular state of each of the switches (S1, . . . , Sn). There is further provided an encoder comprising a plurality of n switches (S1, . . .

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met, and recovering in a recovering step back from any of the nx escalation levels to a previous level or mode, if a de-escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: The present invention relates to an electronic device comprising a first CPU, a second CPU, a first delay stage and a second delay stage for delaying data propagating on a bus, a CPU compare unit, and wherein the first delay stage is coupled to an output of the first CPU and a first input of the CPU compare unit, an input of the first CPU is coupled to a system input bus, the second delay stage is coupled to the system input bus and to an input of the second CPU, an output of the second CPU (CPU2) is coupled to the CPU compare unit, and wherein the first CPU and the second CPU are adapted to execute the same program code and the CPU compare unit is adapted to compare an output signal of the first delay stage, which is a delayed output signal of the first CPU, with an output signal of the second CPU.