Patents by Inventor Rainer Yen-Chieh Huang
Rainer Yen-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917831Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: GrantFiled: August 5, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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FERROELECTRIC MEMORY DEVICES HAVING IMPROVED FERROELECTRIC PROPERTIES AND METHODS OF MAKING THE SAME
Publication number: 20230378354Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Po-Ting LIN, Song-Fu LIAO, Rainer Yen-Chieh HUANG, Hai-Ching CHEN, Yu-Ming LIN, Chung-Te LIN -
Publication number: 20230380177Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.Type: ApplicationFiled: August 2, 2023Publication date: November 23, 2023Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230371272Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11818896Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.Type: GrantFiled: July 26, 2022Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230363173Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Han-Ting Tsai, Tsann Lin, Kuo-Chang Chiang, Min-Kun Dai, Chung-Te Lin
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Publication number: 20230329000Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.Type: ApplicationFiled: June 15, 2023Publication date: October 12, 2023Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11778914Abstract: A thin-film transistor may include an amorphous semiconductor channel layer, an organic material piezoelectric stress gate layer formed adjacent to the amorphous semiconductor channel layer, a source electrode coupled to the organic material piezoelectric stress gate layer, a drain electrode coupled to the organic material piezoelectric stress gate layer and a gate electrode coupled to the organic material piezoelectric stress gate layer. In some embodiments, the amorphous semiconductor channel layer may be amorphous indium gallium zinc oxide. In some embodiments, the organic material piezoelectric stress gate layer may be organic polyvinylidene fluoride. In some embodiments, the amorphous semiconductor channel layer may be formed on a flexible substrate.Type: GrantFiled: April 22, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Rainer Yen-Chieh Huang, Hai-Ching Chen
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Patent number: 11769815Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.Type: GrantFiled: May 13, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20230269947Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.Type: ApplicationFiled: April 10, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer, Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11729990Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.Type: GrantFiled: February 5, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11706928Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFxZr1-xO2. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).Type: GrantFiled: February 3, 2021Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11690228Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: GrantFiled: February 25, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11653501Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.Type: GrantFiled: June 20, 2021Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20230074585Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.Type: ApplicationFiled: November 15, 2022Publication date: March 9, 2023Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11581334Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.Type: GrantFiled: February 5, 2021Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20220384460Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20220375947Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11508755Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.Type: GrantFiled: February 25, 2021Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20220359544Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin