Abstract: A method of enhancing a gross depositional environment (GDE) map of a subsurface formation. The method includes obtaining the GDE map of the subsurface formation, including a lithology map of a plurality of lithotypes and obtaining a paleo-bathymetric map of the subsurface formation. The method further includes assigning an inverse mobility for each of the lithotypes and determining, using a computer processor, an enhanced GDE map based, at least in part, on the GDE map, the paleo-bathymetric map, and the inverse mobility for each of the lithotypes.

Abstract: An elemental analysis of rock samples from outcrop sections or wells is performed. Data quality checks, data analysis, and filtering are performed on the rock samples, including de-spiking of elemental profiles and elemental ratios. First and second derivatives for the elemental profiles and the elemental ratios are calculated. Samples and depths that exceed thresholds are determined. The process is repeated for the elemental profiles and the elemental ratios that are related with boundary determination and carbonate or siliciclastic sediments. Additional filters are applied to at least a subset of the elemental profiles and elemental ratios that are related with boundary determination and carbonate or siliciclastic sediments to enhance the boundary identification. Possible boundaries in depths of the outcrop sections or wells are determined by summarizing the additionally filtered elemental profiles and the additionally filtered elemental ratios.

Abstract: A global objective function is initialized to an initial value. A particular model simulation process is executed using prepared input data. A mismatch value is computed by using a local function to compare an output of the particular model simulation process to corresponding input data for the particular model simulation process. Model objects associated with the particular model simulation process are sent to another model simulation process. An optimization process is executed to predict new values for input data to reduce the computed mismatch value.

Abstract: An elemental analysis of rock samples from outcrop sections or wells is performed. Data quality checks, data analysis, and filtering are performed on the rock samples, including de-spiking of elemental profiles and elemental ratios. First and second derivatives for the elemental profiles and the elemental ratios are calculated. Samples and depths that exceed thresholds are determined. The process is repeated for the elemental profiles and the elemental ratios that are related with boundary determination and carbonate or siliciclastic sediments. Additional filters are applied to at least a subset of the elemental profiles and elemental ratios that are related with boundary determination and carbonate or siliciclastic sediments to enhance the boundary identification. Possible boundaries in depths of the outcrop sections or wells are determined by summarizing the additionally filtered elemental profiles and the additionally filtered elemental ratios.

Abstract: A global objective function is initialized to an initial value. A particular model simulation process is executed using prepared input data. A mismatch value is computed by using a local function to compare an output of the particular model simulation process to corresponding input data for the particular model simulation process. Model objects associated with the particular model simulation process are sent to another model simulation process. An optimization process is executed to predict new values for input data to reduce the computed mismatch value.

Abstract: The present invention teaches an arrangement for increasing the output impedance of a power amplifier coupled to a capacitively loaded line during the switching of power levels by the amplifier on the line. The arrangement of the invention reduces undesired noise voltage during switching. The present invention achieves this end by using a control circuit composed of a differential amplifier which has one input fed from the junction of an impedance resistor and a transistor that simulate the power stage transistor in the power amplifier being switched. This control circuit provides control voltage outputs to power control transistors which are connected to and control the speed of the power stage transistors used to change and discharge the capcitively loaded line.

Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register.

Abstract: Push-pull driver with reduced noise generation resulting from driver switching. A further transistor is arranged between the driver output transistor (which becomes conductive at the low output level) and the chip ground line. Its base is connected to a reference voltage source the other pole of which is connected to the ground plane of the circuit card to which the corresponding semiconductor chip is attached. If a noise voltage is generated on the chip ground line, the emitter potential of the further transistor is pulled up. As its base potential is maintained at a fixed value by the applied reference potential, this transistor becomes less conductive. As a result, the rate of current change in the output stage is reduced. The slowed down current rise, leads to a reduced noise voltage developing on the common chip ground line.

Abstract: Disclosed is a multi-layer module structure having a constant characteristic impedance. In each conductor line plane, two signal lines are arranged between a ground and a voltage supply line. This line sequence: ground/signal/signal/voltage supply line, is repeated several times in each conductor line plane. The spacing between the signal line and the adjacent ground and voltage supply line, respectively, is identical in each case. Adjacent conductor line planes, nth and (n+1)th have conductor lines arranged orthogonally. The lines of the nth and the (n+2)th plane are preferably staggered to each other such that when the nth plane is projected relative to the (n+2)th plane, the ground line of the (n+2)th plane is arranged in between the voltage supply lines (e.g. a voltage supply line and a ground line) of the nth plane.