Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processors can access the memory simultaneously. Additionally, a cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are grouped, and Trellis encoding is performed only of the members of a group. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the computational and memory requirements of the encoder and decoder. Furthermore, Trellis decoding errors are not propagated between the groups.

Abstract: A VDSL system is proposed which operates in a selected one of at least two modes. In one of those modes the volume of data that is to be transmitted is reduced. The invention proposes that this is done in such a way as to reduce the IFFT/FFT computational burden, to give a “low power” transmission mode (in contrast to the “high power” transmission mode in which all the tones are fully used). This also has the advantage that reduced memory is required, especially in the decoder.

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processors can access the memory simultaneously.

Abstract: An optical switching system and method. The method includes tapping a first portion of an incoming data beam from an incoming source; and transferring the incoming data beam from the incoming source to a first path provided by a first MEMS based switching fabric. The method also transfers a monitoring source to monitor a second path of provided by second MEMS based switch fabric, while the second path of the second MEMS based switch fabric is in a stand by mode. A step of tapping a second portion of an outgoing data beam provided by the first MEMS based switching fabric is also included. The method determines if a process condition of the first path by at least the second portion of the outgoing data beam.

Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract: A congestion avoidance scheme for data traffic in ATM networks. The scheme achieves both efficiency and fairness, and exhibits a fast transient response. A congestion avoidance scheme for ATM networks is described which has its optimal operating point at 100% utilization and a fixed, non-zero queue delay. The scheme improves control of end-to-end delay and keeps link utilization of expensive links high despite idle periods in the input load.

Abstract: An explicit rate indication method for congestion management in computer and telecommunication networks. Sources monitor their load and provide the information periodically to switches. The switches, in turn, compute the load level and ask the sources to adjust their rates up or down. The scheme achieves high link utilization, fair allocation of rates among contending sources and provides quick convergence.