Abstract: Compositions comprising the L complex or the M complex of the botulinum neurotoxin E with its associated neurotoxin binding protein(s) (NBP), methods of making, and methods of use to treat pain and wrinkles by injecting locally. Methods of making and isolating the L and M complex comprise a multi-step process of: providing a bacterial cultured media comprising the complex of botulinum neurotoxin E and neurotoxin binding proteins; centrifuging and pelletizing the cultured media; stirring the pelletized culture at 0 to 10° C. over a period of 4 to 24 hours; centrifuging the stirred solution to obtain a supernatant; precipitating the supernatant and filtering to obtain the precipitate; and dissolving the precipitate, centrifuging and filtering to obtain a solution comprising M complex and/or L complex of botulinum neurotoxin E and its NBP; and passing the solution through a functionalized sephadex ion exchange column to isolate the complex.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: A secure electronic marketplace platform is proposed that comprises a server computer equipped with a set of databases, storage systems, payment processing gateway, data analytics engine and a set of user clients to facilitate the sale and purchase of copyrighted digital media entities created by original content creators. Server computer receives a group of one or more copyrighted digital media entities (e.g. digital images) from one group of users and after performing a set of quality assurance related validations, makes them available for purchasing to a second group of users via disclosed platform. By default, limited previews of digital media entities are available via disclosed platform. In addition, users can also purchase a group of one or more digital media entities by registering into the electronic marketplace platform which also requires payment method information.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: A novel automatic standardization and verification process for system design requirements in a product development project is disclosed. In one embodiment, a method for automatic standardization and verification of system design requirements in a product development project using a standardization and verification tool embedded in a computer aided design (CAD) application includes obtaining a desired standardized requirement from a requirements database, retrieving compliance criteria from the standardized requirement, obtaining one or more components associated with the standardized requirement from one or more data sources, and obtaining relevant extracted and derived attributes from the one or more components, associated with the standardized requirement.

Abstract: A novel automatic standardization and verification process for system design requirements in a product development project is disclosed. In one embodiment, a method for automatic standardization and verification of system design requirements in a product development project using a standardization and verification tool embedded in a computer aided design (CAD) application includes obtaining a desired standardized requirement from a requirements database, retrieving compliance criteria from the standardized requirement, obtaining one or more components associated with the standardized requirement from one or more data sources, and obtaining relevant extracted and derived attributes from the one or more components, associated with the standardized requirement.

Abstract: A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

Abstract: This system represents a customizable simulation model of an ATM/SONET Framer for System Level Verification and Performance-Characterization. An Asynchronous Transfer Mode (ATM) data processing ASIC interfaces with a Media Access Control (MAC) device that presents an electrical data path interface, called Universal Test & Operations PHY Interface for ATM (UTOPIA), using ATM protocol on the ASIC side and simplex optical interfaces using Synchronous Optical Network (SONET) protocol on the network side. Such a MAC device, commonly referred to as ATM/SONET Framer, provides one Receive and one Transmit interface to the network at various SONET line rates such as 155.52 Mbps (OC-3), 622.08 Mbps (OC-12), 2488.32 Mbps (OC-48), etc. The ATM and the SONET interfaces operate on different clock frequencies and thus represent two distinct clocking domains. The data interchange between the two clocking domains is achieved via FIFO buffer elements and associated control and status signals.

Abstract: A system, method and computer program features of the present invention, relate to verification or simulation of a design using a behavioral model structure for use in a Client/Server configuration. A physical part presents the external interface, and a functional procedural part which is comprised of at least one VHDL process. A testcase is a set of procedure calls written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.