Patents by Inventor Raj Kumar Singh Parihar

Raj Kumar Singh Parihar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11829764
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: November 28, 2023
    Assignee: MIPS Tech, LLC
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20230205534
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Patent number: 11635963
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 25, 2023
    Assignee: MIPS Tech, LLC
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20210373897
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 2, 2021
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20210357892
    Abstract: A secure electronic marketplace platform is proposed that comprises a server computer equipped with a set of databases, storage systems, payment processing gateway, data analytics engine and a set of user clients to facilitate the sale and purchase of copyrighted digital media entities created by original content creators. Server computer receives a group of one or more copyrighted digital media entities (e.g. digital images) from one group of users and after performing a set of quality assurance related validations, makes them available for purchasing to a second group of users via disclosed platform. By default, limited previews of digital media entities are available via disclosed platform. In addition, users can also purchase a group of one or more digital media entities by registering into the electronic marketplace platform which also requires payment method information.
    Type: Application
    Filed: May 17, 2020
    Publication date: November 18, 2021
    Inventors: Akanksha Srivastava, Satyam Srivastava, Raj Kumar Singh Parihar
  • Patent number: 11080062
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 3, 2021
    Assignee: MIPS Tech, LLC
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
  • Publication number: 20200225955
    Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar