Abstract: An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.

Abstract: A single-port memory cell arrangement includes a multiplicity of single-port memory cells, each having a selection transistor and a memory transistor. The selection transistor has a control terminal connected to a word line, and a load-path connected to a data line. The memory transistor has a control terminal connected to a supply potential, and a load-path connected to the second end of the selection-transistor's load-path. The memory transistor is configured to switch, in response to a signal on the data line, between first and second potentials corresponding to two memory states. These potentials and the supply potential are selected such that first and second ends of the memory-transistor-load-path are at the same potential. The memory cell also includes a controllable switch having a first terminal connected to a supply line, and a second terminal connected to the second end of the memory-transistor-load-path.

Abstract: A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the word lines comprise a negative voltage to reduce leakage current from the memory cell.

Abstract: A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to a second terminal of the storage transistor is disclosed. The access transistors serve as access ports for the memory cell.

Abstract: In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed during the same cycle. In another embodiment, dual port memory cells are employed to enable a second row of memory cells to be refreshed during the same cycle.

Abstract: An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a plurality of comparator units. In one embodiment, a comparator unit is coupled to a memory bank to facilitate parallel testing.

Abstract: A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the first and second ports. A refresh operation is performed through one of said ports. When a refresh operation is performed through said one port, a read operation can be performed through the cache memory in parallel.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The storage transistor comprises a gate oxide formed from a material having a high dielectric constant to increase the capacitance.

Abstract: A method and system for streaming media data to a fixed client and/or a mobile client. In one method embodiment, the present invention recites encoding media data to be streamed to a client into a first multiple description bitstream and into a second multiple description bitstream. The present embodiment then recites distributing the first and second multiple description bitstreams to a plurality of servers placed at intermediate nodes throughout a network such that a client is provided with access to the media data via a plurality of transmission paths.

Abstract: A method and system for streaming media data to a fixed client and/or a mobile client. In one method embodiment, the present invention recites encoding media data to be streamed to a client into a first multiple description bitstream and into a second multiple description bitstream. The present method then determines the appropriate plurality of servers from a network of servers onto which the first and second multiple description bitstreams should be distributed. The present embodiment then recites distributing the first and second multiple description bitstreams to the appropriate plurality of servers positioned at intermediate nodes throughout a network such that a client is provided with access to the media data via a plurality of transmission paths. The present method is also well suited to redistribution of multiple description bitstreams to servers based upon time-varying demand, client movement, and the like.

Abstract: The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.

Abstract: An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.

Abstract: A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the word lines comprise a negative voltage to reduce leakage current from the memory cell.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The storage transistor comprises a gate oxide formed from a material having a high dielectric constant to increase the capacitance.

Abstract: A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to a second terminal of the storage transistor is disclosed. The access transistors serve as access ports for the memory cell.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. A boosted voltage is coupled to the gate of the storage transistor to increase the charge stored in the memory cell, thereby improving retention time.