Abstract: A duty-cycle correction (DCC) circuit adapted to adjust the duty cycle of a differential clock signal to conform it to the requirements of a half-rate clocking system. In a representative embodiment, the DCC circuit has a buffer circuit adapted to generate a differential output clock signal by adding offset voltage to a differential input clock signal. A feedback loop coupled to the buffer circuit processes the output clock signal to evaluate deviation of its duty-cycle value from 50% and, based on the evaluation, configures the buffer circuit to adjust the offset voltage such that the duty-cycle deviation is reduced. The feedback loop and the buffer circuit are controlled by a duty-cycle calibration engine, e.g., a digital logic circuit adapted to determine an appropriate value for the offset voltage, which causes the duty-cycle value in the output clock signal to be substantially 50% regardless of the duty-cycle value in the input clock signal.

Abstract: A duty-cycle correction (DCC) circuit adapted to adjust the duty cycle of a differential clock signal to conform it to the requirements of a half-rate clocking system. In a representative embodiment, the DCC circuit has a buffer circuit adapted to generate a differential output clock signal by adding offset voltage to a differential input clock signal. A feedback loop coupled to the buffer circuit processes the output clock signal to evaluate deviation of its duty-cycle value from 50% and, based on the evaluation, configures the buffer circuit to adjust the offset voltage such that the duty-cycle deviation is reduced. The feedback loop and the buffer circuit are controlled by a duty-cycle calibration engine, e.g., a digital logic circuit adapted to determine an appropriate value for the offset voltage, which causes the duty-cycle value in the output clock signal to be substantially 50% regardless of the duty-cycle value in the input clock signal.