Patents by Inventor Raj N. Master

Raj N. Master has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7544542
    Abstract: Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: June 9, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Raj N. Master, Jacquana Diep, Mohammad Khan
  • Publication number: 20080227310
    Abstract: Various sockets for packaged integrated circuits and methods of making the same are provided. In one aspect, a method of mounting a semiconductor chip is provided that includes providing a package that has a base substrate with a first side and a second side opposite the first side. The second side has a central region. The package includes a semiconductor chip and a lid coupled to the first side. A socket is provided for receiving the base substrate. The socket includes a mound that projects toward the second side of the base substrate when the base substrate is seated in the socket to provide support for the central region of the base substrate. The package is mounted in the socket. The mound provides support for the central region of the base substrate.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 18, 2008
    Inventors: Seah Sun Too, Raj N. Master, Jacquana Diep, Mohammad Khan
  • Publication number: 20080124841
    Abstract: Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.
    Type: Application
    Filed: August 7, 2006
    Publication date: May 29, 2008
    Inventors: Seah Sun Too, Raj N. Master, Jacquana Diep, Mohammad Khan
  • Publication number: 20070284737
    Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 13, 2007
    Inventors: Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
  • Patent number: 7215030
    Abstract: A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 8, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Srinivasan Ashok Anand, Srinivasan Parthasarathy, Yew Cheong Mui
  • Patent number: 6812570
    Abstract: An organic carrier member for mounting a semiconductor device is provided that has a plurality of solder pads containing low amounts of tin and bismuth. Embodiments include a bismaleimide-triazine epoxy laminate having a plurality of solder pads on the surface thereof where the solder pads contain no more than about 20 weight percent tin and has a reflow temperature of no greater than about 270° C.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Zubair Khan, Maria Guardado, Charles Anderson
  • Patent number: 6722553
    Abstract: A method and apparatus are provided for controllably dispensing flux on a substrate having a plurality of conductive terminals. Flux having a viscosity range between 10 centipoises and about 150 centipoises is sprayed on the substrate and the conductive terminals at a valve pressure range between about 1.5 psi and about 30 psi via a dispense nozzle of a flux dispenser. Upon a subsequent high temperature solder reflow process, the sprayed flux on the substrate is mostly removed by thermal decomposition to volatile species, thereby significantly reducing flux residue remaining on the surface of the substrate between the conductive terminals.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Z. Khan, Maria G. Guardado, Ooi Tong Ong
  • Patent number: 6709963
    Abstract: A method and an apparatus are provided for selectively depositing flux on a plurality of flip-chip bumps arranged on a semiconductor chip by jet printing a flux pattern, which is substantially identical to the arrangement pattern of the flip-chip bumps. The flux pattern is determined by measuring the chip configuration and converting the configuration to computer-recognizable data. The converted chip configuration is stored in data storage, and a jet printing head prints the flux pattern based on the computer-recognizable data. A conveyance plate is provided to transport the semiconductor chip to a flux-deposition area below the jet printing head.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: March 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan D. Halderman, Raj N. Master
  • Patent number: 6632690
    Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: October 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Edward S. Alcid, Diong-Hing Ding
  • Patent number: 6617195
    Abstract: A method of manufacturing a semiconductor device by attaching a flip chip die to an organic substrate using solder comprises applying no-clean flux to the flip chip die or the organic substrate; heating the flip chip die and the organic substrate to bond the flip chip die to the organic substrate, and cooling the flip chip die and the organic substrate. The step of heating the flux includes controlling oxygen and moisture content of an atmosphere surrounding the flux, preheating to a temperature of about 145° C. to about 165° C., soaking at a temperature of about 145° C. to about 165° C. for about four to about six minutes, and reflowing above the solder's melting point.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: September 9, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Z. Khan, Maria G. Guardado
  • Patent number: 6591992
    Abstract: A boat for cleaning semiconductor packages, including cleaning ball grid array packages in centrifugal cleaners. The boat includes a bottom plate with receptacles for receiving semiconductor packages and a top plate having through holes, where each through hole is smaller than the receptacle with which it corresponds in the bottom plate. An alignment mechanism ensures that the top plate is aligned with the bottom plate in a manner that results in each through hole being positioned directly over a respective one of the receptacles. An attachment mechanism releasably attaches the top plate to the bottom plate in a co-planar relationship that results in the presence of a vertical space between the two plates.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: July 15, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ajit M. Dubey, Raj N. Master, Ong Ot, Chan Cs
  • Publication number: 20030077852
    Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.
    Type: Application
    Filed: February 5, 2002
    Publication date: April 24, 2003
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Edward S. Alcid, Diong-Hing Ding
  • Patent number: 6536649
    Abstract: Residue contaminates semiconductor devices during processing in a furnace. Residue contamination is prevented by removing the residue before it builds up to a point where it can contaminate semiconductor devices. Residue build-up is monitored using a residue build-up monitoring device mounted on the furnace exhaust stack. When residue build-up reaches a predetermined level a signal is generated by the residue build-up monitoring device notifying technicians that furnace cleaning is required.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Jonathan D. Halderman
  • Publication number: 20030052155
    Abstract: A universal attach manufacturing process employs a boat onto which solder balls or columns are loaded. A universal attach line has a number of attach station to accommodate different types of attach processes. Depending on the process and the desired configuration and form factor of the array of solder balls or columns, a template is selected that covers some of the holes in the universal boat, and exposes other holes. The solder balls or columns are held securely in the exposed holes, and a substrate is placed onto the solder balls. Once loaded with balls or columns, the universal boat is transported to only the appropriate attach stations in the universal attach line, where the different attach operations for a given attach process, such as high temperature ball attach, eutectic ball attach, or column attach, are performed.
    Type: Application
    Filed: February 5, 2002
    Publication date: March 20, 2003
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Cheon-Seng Chan, Ooi-Tong Ong
  • Publication number: 20030047527
    Abstract: A boat onto which solder balls or columns are loaded for an attach process can be used in a universal attach line has a number of attach station to accommodate different types of attach processes. Depending on the process and the desired configuration and form factor of the array of solder balls or columns, a template is selected that covers some of the holes in the universal boat, and exposes other holes. The holes are configured and sized to hold solder balls in the holes such that the solder balls protrude above the top surface of the boat by a predetermined height. This prevents damage to the solder balls while ensuring that the solder balls protrude enough to accommodate imperfectly flat packages that are placed on the array of solder balls held in the boat. Vacuum applied through the holes help to securely hold the balls in place, and a substrate is placed onto the solder balls.
    Type: Application
    Filed: February 5, 2002
    Publication date: March 13, 2003
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Cheon-Seng Chan
  • Publication number: 20030037959
    Abstract: An organic carrier member for mounting a semiconductor device is provided that has a plurality of solder pads containing low amounts of tin and bismuth. Embodiments include a bismaleimide-triazine epoxy laminate having a plurality of solder pads on the surface thereof where the solder pads contain no more than about 20 weight percent tin and has a reflow temperature of no greater than about 270° C.
    Type: Application
    Filed: June 28, 2002
    Publication date: February 27, 2003
    Inventors: Raj N. Master, Mohammed Zubair Khan, Maria Guardado, Charles Anderson
  • Patent number: 6488158
    Abstract: A boat is formed with a plurality of through-holes sized to securely maintain ceramic or organic flip chip semiconductor packages in place during assembly. Embodiments comprises a boat having a bottom layer with an array of four-sided through-holes and a top layer with an array of through-holes and tabs extending from the sides of the through-hole. Embodiments further include a boat having a bottom layer with through-holes smaller than substantially aligned overlying through-holes in the top layer, the substantially aligned through-holes forming flip chip package holding pockets. An alignment mechanism ensures that components are accurately positioned on flip chip packages held in the boat during assembly.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: December 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohammad Khan, Raj N. Master, Maria G. Guardado, Loo L. Teoh, Ahmad Juwanda
  • Publication number: 20020170746
    Abstract: An organic carrier member for mounting a semiconductor device is provided that has a plurality of solder pads containing low amounts of tin. Embodiments include a bismaleimide-triazine epoxy laminate having a plurality of solder pads on the top surface thereof where the solder pads contain no more than about 20 weight percent tin and has a reflow temperature of no greater than about 270° C.
    Type: Application
    Filed: January 13, 2000
    Publication date: November 21, 2002
    Inventors: RAJ N MASTER, MOHAMMED ZUBAIR KHAN, MARIA GUARDADO, CHARLES ANDERSON
  • Patent number: 6446818
    Abstract: A boat for cleaning semiconductor packages, including cleaning ball grid array packages in centrifugal cleaners. The boat includes a bottom plate with receptacles for receiving semiconductor packages and a top plate having through holes, where each through hole is smaller than the receptacle with which it corresponds in the bottom plate. An alignment mechanism ensures that the top plate is aligned with the bottom plate in a manner that results in each through hole being positioned directly over a respective one of the receptacles. An attachment mechanism releasably attaches the top plate to the bottom plate in a co-planar relationship that results in the presence of a vertical space between the two plates.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ajit M. Dubey, Raj N. Master, Ot Ong, C S Chan
  • Patent number: 6409070
    Abstract: A method of manufacturing a flip-chip semiconductor device by attaching a semiconductor die to a substrate using solder comprises the steps of applying a no-clean flux to the semiconductor die and the substrate; heating the solder and the flux in a furnace to bond the semiconductor die to the substrate; and underfilling between the semiconductor die and the substrate. While the solder and flux is being heated, a reducing atmosphere in the furnace is being measured to determine the moisture content. When the moisture content exceeds a threshold amount, a signal will be provided. A reflow furnace for practicing the method is also disclosed.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: June 25, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Z. Khan, Maria G. Guardado, Diong Hing Ding, Junaida Abu Bakar