Patents by Inventor Raj Narasimhan
Raj Narasimhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961118Abstract: The present invention relates to methods and systems for targeting and retargeting individuals with advertisement spots during television broadcasting. The method and system enable an advertiser for identifying and categorizing a set of viewers or individuals for retargeting advertisement based on parameters such as, but not limited to, interests or preferences of the individuals, past purchases and interactions of the individuals with the advertiser. The method and system further enable the advertiser to segregate the plurality of individuals into subgroups on the basis of information such as, but not limited to, demography, psychographic and behavioral characteristics of the plurality of individuals. The method and system then enable the advertiser to define one or more advertisement spots and corresponding advertisements to be delivered to different sub groups of individuals based on the categorization.Type: GrantFiled: April 28, 2022Date of Patent: April 16, 2024Assignee: Adcuratio Media, Inc.Inventors: Harish Narasimhan, Raj P. Kiran, Vivek Maheshwari, Adam Kauppi, Dan Coronel, Ranjan Damodar
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Patent number: 11924916Abstract: A user equipment (UE) is configured to transmit, to a cellular carrier, a request to activate the UE with the cellular carrier. The UE is also configured to, in response to receiving an authentication request for authenticating a user of the UE, transmit, to the cellular carrier, information identifying another UE and authentication information for authenticating the user ; prompt the user, via a display of the UE, to provide, to an input system of the UE, verification information transmitted to the other UE; transmit, to the cellular carrier, the verification information; and in response to validation of the verification information by the cellular carrier, receive an embedded subscriber identity module (eSIM) subscription transferred from the other UE.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Raj S. Chaugule, Alex M. Was, Avinash Narasimhan, Damien R. Holzapfel, He Zheng, Li Li, Timothy M. Sheridan, Vikram B. Yerrabommanahalli
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Patent number: 6636415Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.Type: GrantFiled: July 17, 2002Date of Patent: October 21, 2003Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Raj Narasimhan
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Publication number: 20020176220Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.Type: ApplicationFiled: July 17, 2002Publication date: November 28, 2002Inventors: Sanh D. Tang, Raj Narasimhan
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Patent number: 6472321Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions herein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.Type: GrantFiled: January 15, 2002Date of Patent: October 29, 2002Assignee: Micron Technology, Inc.Inventors: Anand Srinivasan, Sujit Sharon, Raj Narasimhan
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Patent number: 6433994Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.Type: GrantFiled: May 11, 2001Date of Patent: August 13, 2002Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Raj Narasimhan
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Publication number: 20020058413Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions therein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.Type: ApplicationFiled: January 15, 2002Publication date: May 16, 2002Inventors: Anand Srinivasan, Sujit Sharon, Raj Narasimhan
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Patent number: 6376380Abstract: The invention includes methods of forming memory circuitry, including methods of forming memory circuitry comprising a buried bit line array of memory cells. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells includes, in a single planarizing step, planarizing storage node contact opening plugging material and bit line trench plugging material to insulating material to form bit lines and storage node contacts which are electrically isolated laterally from one another by the insulating material. In one implementation, a method of forming memory circuitry comprising a buried bit line array of memory cells, includes forming word lines over a semiconductor substrate. An insulating layer is formed over the substrate and over the word lines. Using a single photomasking step, bit line contact openings and capacitor storage node contact openings are patterned and formed into the insulating layer.Type: GrantFiled: August 30, 2000Date of Patent: April 23, 2002Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Raj Narasimhan
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Patent number: 6365515Abstract: The present invention relates to chemical vapor deposition processes related to the manufacture of integrated circuit devices. In accordance with one embodiment of the present invention, a process for forming an electrical contact to a silicon substrate is provided wherein a semiconductor wafer is positioned in a reaction chamber wherein the semiconductor wafer includes an insulating layer disposed over a semiconductor substrate, and the insulating layer defines a contact opening therein. The contact opening defines insulating side wall regions therein. The insulating side walls extend from an upper surface region of the insulating layer to an exposed semiconductor region of the semiconductor substrate. A set of reactants are introduced into the reaction chamber, RF plasma is generated in the vicinity of the semiconductor wafer, and the temperature and pressure of the reaction chamber is regulated.Type: GrantFiled: August 28, 2000Date of Patent: April 2, 2002Assignee: Micron Technology, Inc.Inventors: Anand Srinivasan, Sujit Sharon, Raj Narasimhan
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Patent number: 6335237Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.Type: GrantFiled: March 3, 2000Date of Patent: January 1, 2002Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Raj Narasimhan
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Publication number: 20010030845Abstract: The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced electrical nodes. The bitline layer comprises at least one conductive material. Openings are etched through the bitline layer and to the electrical nodes. After the openings are formed, the bitline layer is patterned into bitlines. The invention also encompasses a method of forming a capacitor and bitline structure. A substrate is provided, and comprises a plurality of spaced electrical nodes. A stack of bitline materials is formed over at least some of the spaced electrical nodes. The bitline materials comprise at least one insulative material over at least one conductive material. Openings are etched through the bit line materials and to the electrical nodes. Conductive masses are formed in at least some of the openings. After the conductive masses are formed, the bitline materials are patterned into bitlines.Type: ApplicationFiled: May 11, 2001Publication date: October 18, 2001Inventors: Sanh D. Tang, Raj Narasimhan