Patents by Inventor Raj Yavatkar

Raj Yavatkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7457296
    Abstract: A method and apparatus for sorting packets by packet schedulers using a connected trie data structure is described. According to one embodiment of the invention, the packet scheduler receives a packet on a network and assigns the packet a time stamp value. The packet is inserted into a trie data structure that represents a scheduling horizon and includes a plurality of packets. The packet scheduler transmits the packet over the network based on its sorted order within the trie data structure.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: November 25, 2008
    Assignee: Intel Corporation
    Inventors: Michael Kounavis, Alok Kumar, Raj Yavatkar
  • Patent number: 7441272
    Abstract: A technique for self-isolation of a network device that has been identified as potentially harmful. The network device may be isolated from the network except for an out-of-band communication channel that can be used for management purposes to restore or repair the device prior to the network connection being re-established.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: David M. Durham, Ravi Sahita, Priya Rajagopal, James Kardach, Scott Hahn, Raj Yavatkar
  • Patent number: 7411902
    Abstract: A method and system for maintaining partial order of packets in packet processing modules is described. The system includes a memory and a plurality of packet processing modules to process packets that are part of a sequence in order. The memory stores a plurality of indicators, each indicator associated with one of the plurality of packet processing modules to identify which packets in the sequence are to be processed by the packet processing module and which packets in the sequence are to be skipped. The next packet in the sequence to be processed by the packet processing module is determined based on the stored indicators. A packet received at the packet processing module is processed if the packet is the next packet in the sequence to be processed.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Alok Kumar, Benjamin C. Hardekopf, Raj Yavatkar
  • Patent number: 7408932
    Abstract: A method and apparatus for two-stage packet classification, the two-stage packet classification scheme including a first stage and a second stage. In the first classification stage, a packet is classified on the basis of the packet's network path. In the second stage of classification, the packet is classified on the basis of one or more transport (or other) fields of the packet. Also disclosed are embodiments of most specific filter matching and transport level sharing, and either one or both of these techniques may be implemented in the two-stage classification method.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: August 5, 2008
    Assignee: Intel Corporation
    Inventors: Michael E. Kounavis, Alok Kumar, Raj Yavatkar, Harrick M. Vin
  • Patent number: 7394809
    Abstract: A packet classifier having a forest of hash tables data structure. The forest of hash tables data structure includes a number of hash tables, each hash table having a bit mask corresponding to an equivalent set of rules. Each hash table includes a number of entries, wherein an entry of a hash table may correspond to a rule. One or more of the hash tables may include a marker in one entry, wherein the marker identifies another one of the hash tables. The hash table identified by the marker is a descendant of the hash table in which the marker is placed.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: July 1, 2008
    Assignee: Intel Corporation
    Inventors: Alok Kumar, Raj Yavatkar
  • Publication number: 20080104325
    Abstract: A method and apparatus for placement of temporary relevant data are disclosed. In one embodiment, the apparatus comprising one or more memories through which a producer provides data for access by a consumer in a memory-based producer-consumer relationship, and an agent to monitor access by the producer and consumer to the one or more memories and to direct placement of produced data into at least one of the one or more memories that is closer to the consumer, wherein placement occurs at a time determined by the agent.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 1, 2008
    Inventors: Charles Narad, Raj Yavatkar
  • Patent number: 7246205
    Abstract: Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be implemented in software and/or hardware, monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Santosh Balakrishnan, Raj Yavatkar, Charles Narad
  • Patent number: 7203740
    Abstract: A computer system for allowing proprietary forwarding elements to interoperate with standard control elements in an open network architecture. The computer system comprises a forwarding element that is adapted to perform data forwarding functions in a computer network. A control element is adapted to perform network signaling and control functions in the computer network. The control element is adapted to generate a standardized data set for configuring the forwarding element. An interconnecting element operatively connects the forwarding element to the control element. A forwarding element plugin is integrated with the control element for receiving the standardized data set from the control element, translating the standardized data set into a specialized data set, and transmitting the specialized data set to the forwarding element to configure the forwarding element.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: David Putzolu, Raj Yavatkar, Bernard N. Keany
  • Patent number: 7142541
    Abstract: According to some embodiments, routing information for an information packet is determined in accordance with a destination address and a device address.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: November 28, 2006
    Assignee: Intel Corporation
    Inventors: Alok Kumar, Raj Yavatkar
  • Publication number: 20060153184
    Abstract: Reducing memory access bandwidth consumption in a hierarchical packet scheduler. A hierarchical packet scheduler is maintained, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers, wherein one or more threads serve each level. Scheduling operations are performed at each scheduler of the hierarchical packet scheduler by reading a portion of scheduler state from external memory.
    Type: Application
    Filed: December 27, 2004
    Publication date: July 13, 2006
    Inventors: Michael Kounavis, Alok Kumar, Raj Yavatkar
  • Publication number: 20060140201
    Abstract: A hierarchical packet scheduler using hole-filling and multiple packet buffering. Packet references are enqueued into a hierarchical packet scheduler, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers being served by one or more threads, wherein the number of threads serving a particular level is not dependent on the number of schedulers on the particular level. Packet references are dequeued from the hierarchical packet scheduler at a root level scheduler of the one or more schedulers.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Inventors: Alok Kumar, Michael Kounavis, Raj Yavatkar
  • Publication number: 20060136671
    Abstract: Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be implemented in software and/or hardware, monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Inventors: Santosh Balakrishnan, Raj Yavatkar, Charles Narad
  • Publication number: 20060095551
    Abstract: Embodiments of the invention are generally directed to a system and method for a service processor architecture. The service processor provides an extensible execution environment for a platform (or other device) that is accessible when the host system is non-functional. In an embodiment, the service processor has one or more platform-independent external interfaces to provide a communications link between the service processor and one or more management resources.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: John Leung, David Durham, Raj Yavatkar, Milan Milenkovic, Mark Doran, Greg Gans, Paul Crutcher
  • Publication number: 20060095961
    Abstract: Method, apparatus, and system for isolating potentially vulnerable nodes of a network. In one embodiment a network is partitioned into subnets of varying levels of security. A client device may be assigned a network access assignment through one of the subnets based on a level of vulnerability assessed for the client device. The level of vulnerability may be determined based on compliance of the client device with available upgrades and/or patches.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Priya Govindarajan, Ravi Sahita, Dylan Larson, David Durham, Raj Yavatkar
  • Publication number: 20060067325
    Abstract: A method and apparatus for sorting packets by packet schedulers using a connected trie data structure is described. According to one embodiment of the invention, the packet scheduler receives a packet on a network and assigns the packet a time stamp value. The packet is inserted into a trie data structure that represents a scheduling horizon and includes a plurality of packets. The packet scheduler transmits the packet over the network based on its sorted order within the trie data structure.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Michael Kounavis, Alok Kumar, Raj Yavatkar
  • Publication number: 20060005245
    Abstract: A technique for self-isolation of a network device that has been identified as potentially harmful. The network device may be isolated from the network except for an out-of-band communication channel that can be used for management purposes to restore or repair the device prior to the network connection being re-established.
    Type: Application
    Filed: June 9, 2004
    Publication date: January 5, 2006
    Inventors: David Durham, Ravi Sahita, Priya Rajagopal, James Kardach, Scott Hahn, Raj Yavatkar
  • Publication number: 20050278563
    Abstract: Method and Apparatuses for determining integrity of a platform and notifying a remote system. In one embodiment a verification agent accesses a portion of a memory on the platform at initialization of the platform to determine if the data has been compromised or corrupted. The verification agent causes the information to be transmitted to a remote system. The verification agent may be local to the platform for which integrity is determined, and transmit the information to a remote administrator. Alternatively, the agent may access the platform over a bus or private channel, or a network connection and indicate information regarding the verification process to an entity remote to the tested platform.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 15, 2005
    Inventors: David Durham, Travis Schluessler, Raj Yavatkar, Vincent Zimmer, Carey Smith
  • Publication number: 20050278499
    Abstract: A method and apparatus for cross validation of data using multiple subsystems are described. According to one embodiment of the invention, a computer comprises a first subsystem and a second subsystem; and a memory, the memory comprising a first memory region and a second memory region, the first memory region being associated with the first subsystem and a second memory region being associated with the second subsystem; upon start up of the computer, the first subsystem to validate the second memory region and the second subsystem to validate the first memory region.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 15, 2005
    Inventors: David Durham, Travis Schluessler, Raj Yavatkar, Vincent Zimmer, Carey Smith
  • Publication number: 20050276228
    Abstract: Techniques for self-isolation of a network device that has been identified as potentially harmful. The network device may be isolated from the network except for an out-of-band communication channel that can be used for management purposes to restore or repair the device prior to the network connection being re-established.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 15, 2005
    Inventors: Raj Yavatkar, Alan Crouch, David Durham
  • Publication number: 20050226235
    Abstract: A method and apparatus for two-stage packet classification. In the first stage, which may be implemented in software, a packet is classified on the basis of the packet's network path and, perhaps, its protocol. In the second stage, which may be implemented in hardware, the packet is classified on the basis of one or more transport level fields of the packet. An apparatus of two-stage packet classification may include a processing system for first stage code execution, a classification circuit for performing the second stage of classification, and a memory to store a number of bins, each bin including one or more rules.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Alok Kumar, Michael Kounavis, Raj Yavatkar, Prashant Chandra, Sridhar Lakshmanamurthy, Chen-Chi Kuo, Harrick Vin