Patents by Inventor Raja Bilwakeshwar Ivaturi

Raja Bilwakeshwar Ivaturi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scalable connectivity verification using conditional cut-points
    Patent number: 10970454
    Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi
  • SCALABLE CONNECTIVITY VERIFICATION USING CONDITIONAL CUT-POINTS
    Publication number: 20200143101
    Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi
  • Scalable connectivity verification using conditional cut-points
    Patent number: 10579770
    Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi
  • SCALABLE CONNECTIVITY VERIFICATION USING CONDITIONAL CUT-POINTS
    Publication number: 20190286782
    Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi